• Multiply and divide an incoming clock (DFS).
• Recondition a clock to, for example, ensure 50% duty cycle
  Duty cycle
  In engineering, the duty cycle of a machine or system is the time that it spends in an active state as a fraction of the total time under consideration....
  
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• Phase shift (DLL).
• Eliminate clock skew
  Clock skew
  -In circuit design:In circuit designs, clock skew is a phenomenon in synchronous circuits in which the clock signal arrives at different components at different times...
  
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See also

• Clock signal
  Clock signal
  In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...
  
  
• Delay-locked loop
  Delay-locked loop
  In electronics, a delay-locked loop is a digital circuit similar to a phase-locked loop , with the main difference being the absence of an internal voltage-controlled oscillator...
  
  
• Phase-locked loop
  Phase-locked loop
  A phase-locked loop or phase lock loop is a control system that generates an output signal whose phase is related to the phase of an input "reference" signal. It is an electronic circuit consisting of a variable frequency oscillator and a phase detector...
  
  
• Field-programmable gate array
  Field-programmable gate array
  A field-programmable gate array is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable"...
  
  (DCM is used in FPGA)