XAP processor
Encyclopedia
The XAP processor is a RISC processor
architecture developed by Cambridge Consultants Ltd
since 1994. XAP processors are a family of 16-bit
and 32-bit
cores, all of which are intended for use in an application-specific integrated circuit
or ASIC
chip design. XAP processors were designed for use in mixed-signal integrated circuits for sensor
or wireless
applications including Bluetooth
, ZigBee
, GPS, RFID or Near Field Communication
chips. Typically these integrated circuits are used in low cost, high volume products that are battery-powered and must have low energy consumption. There are other applications where XAP processors have been used to good effect, such as wireless sensor networks and medical devices, e.g. hearing aids.
, 16-bit processor with a 16-bit data bus and an 18-bit instruction bus
intended for running programs stored in on-chip read-only memory
or ROM. Data and instructions were each addressed by separate 16-bit address bus
.
or other off-chip memories. Large programs were accommodated by a 24-bit address bus for instructions and there was a 16-bit address bus for data. XAP2 was a 12,000-gate processor with support for interrupts and a software tool chain including a C
compiler
and the XAPASM assembler for its assembly language
. XAP2 was also used in Cambridge Consultants' ASIC designs and it was also provided to other semiconductor companies as a semiconductor intellectual property core
, or IP core.
XAP2 was adopted by three fabless semiconductor companies
that emerged from Cambridge Consultants: CSR plc
(Cambridge Silicon Radio) is the main provider of Bluetooth chips for mobile phones and headsets; Ember Corporation is a leading supplier of ZigBee chips; and Cyan Technology supplies XAP2-powered microcontrollers. As a consequence, and combined with other licensees and Cambridge Consultants’ ASIC projects, there are now over one billion (1,000 million) XAP processors in use worldwide.
semiconductor process technologies at 0.13 micrometre and below. This led Cambridge Consultants’ engineers to make certain design decisions including the use of a Von Neumann architecture
, unified data and address bus, that enabled both the program's instructions and constants data to be held in a single on-chip memory. The program memory was to be either Flash
or one-time programmable EPROM
and ASIC design is considerably simplified if a single memory is used without the need to pre-determine the split between instructions and fixed data. The XAP3's instruction set design also focussed on high code density to reduce the size of the program memory, thereby reducing cost and also the energy consumed by instruction fetches.
MIPS
when clocked at 80 MHz.
XAP4 was designed for use in modern ASIC or microcontroller
applications capable of processing real-world data captured by an Analog to digital converter (ADC) or similar sources. The processor's 16-bit integer word supports the precision of most ADCs without carrying the overhead of a 32-bit processor. XAP4 also offers a migration path from 8-bit processors, such as 8051
, in applications that need increased performance and program size, but cannot justify the cost and overhead of a 32-bit processor.
, which maximises their performance when clocked at low frequencies. This is tailored to the requirements of small, low-energy ASICs as it minimises processor hardware size (the XAP5 core uses 18,000-gates), and it fits designs that are clocked relatively slowly to reduce an ASIC's dynamic power consumption and run programs direct from Flash or OTP memory that has a slow access time. Typical clock speeds for XAP5 are in the range of 16 to 100 MHz on a 0.13 process. XAP5 has particular design features making it suitable for executing programs from Flash including a Vector Pointer and an Address Translation Window, which combine to allow in-place execution of programs and relocation of programs regardless of where they are stored in physical memory.
and with a fast interrupt
response. Consequently the processors are designed with hardware and instruction set support for protected software operating modes that partition user code from privileged operating system and interrupt handler code. The XAP processor hardware manages the mode transitions and call stack
in response to events and this approach ensures a fast and deterministic interrupt response. The protected operating modes enable a system on a chip to be designed that is a secure or trustworthy system and offers high availability
.
The current XAP processors are designed using the Verilog
hardware description language and provided as RTL
code ready for logic simulation
and logic synthesis
with a test bench
. They are supported with Cambridge Consultants’ xIDE software development tools and SIF debug technology. These processors and tools enable functional verification
and software verification
that reduces the project risk, accelerates time-scales and cuts cost of ownership, especially for software engineering.
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
architecture developed by Cambridge Consultants Ltd
Cambridge Consultants Ltd
Cambridge Consultants is an international technology development and consultancy company, providing outsourced Research and Development to clients - from start-ups to blue-chip multinationals - who need to develop innovative, technologically novel, breakthrough products...
since 1994. XAP processors are a family of 16-bit
16-bit
-16-bit architecture:The HP BPC, introduced in 1975, was the world's first 16-bit microprocessor. Prominent 16-bit processors include the PDP-11, Intel 8086, Intel 80286 and the WDC 65C816. The Intel 8088 was program-compatible with the Intel 8086, and was 16-bit in that its registers were 16...
and 32-bit
32-bit
The range of integer values that can be stored in 32 bits is 0 through 4,294,967,295. Hence, a processor with 32-bit memory addresses can directly access 4 GB of byte-addressable memory....
cores, all of which are intended for use in an application-specific integrated circuit
Application-specific integrated circuit
An application-specific integrated circuit is an integrated circuit customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC...
or ASIC
ASIC
ASIC may refer to:* Application-specific integrated circuit, an integrated circuit developed for a particular use, as opposed to a customised general-purpose device.* ASIC programming language, a dialect of BASIC...
chip design. XAP processors were designed for use in mixed-signal integrated circuits for sensor
Sensor
A sensor is a device that measures a physical quantity and converts it into a signal which can be read by an observer or by an instrument. For example, a mercury-in-glass thermometer converts the measured temperature into expansion and contraction of a liquid which can be read on a calibrated...
or wireless
Wireless
Wireless telecommunications is the transfer of information between two or more points that are not physically connected. Distances can be short, such as a few meters for television remote control, or as far as thousands or even millions of kilometers for deep-space radio communications...
applications including Bluetooth
Bluetooth
Bluetooth is a proprietary open wireless technology standard for exchanging data over short distances from fixed and mobile devices, creating personal area networks with high levels of security...
, ZigBee
ZigBee
ZigBee is a specification for a suite of high level communication protocols using small, low-power digital radios based on an IEEE 802 standard for personal area networks. Applications include wireless light switches, electrical meters with in-home-displays, and other consumer and industrial...
, GPS, RFID or Near Field Communication
Near Field Communication
Near field communication, or NFC, allows for simplified transactions, data exchange, and wireless connections between two devices in proximity to each other, usually by no more than a few centimeters. It is expected to become a widely used system for making payments by smartphone in the United States...
chips. Typically these integrated circuits are used in low cost, high volume products that are battery-powered and must have low energy consumption. There are other applications where XAP processors have been used to good effect, such as wireless sensor networks and medical devices, e.g. hearing aids.
XAP1
The first XAP processor was XAP1, designed in 1994 and used for a number of wireless and sensor ASIC projects at Cambridge Consultants. It was a very small, 3,000-gate, Harvard architectureHarvard architecture
The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. The term originated from the Harvard Mark I relay-based computer, which stored instructions on punched tape and data in electro-mechanical counters...
, 16-bit processor with a 16-bit data bus and an 18-bit instruction bus
Instruction set
An instruction set, or instruction set architecture , is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O...
intended for running programs stored in on-chip read-only memory
Read-only memory
Read-only memory is a class of storage medium used in computers and other electronic devices. Data stored in ROM cannot be modified, or can be modified only slowly or with difficulty, so it is mainly used to distribute firmware .In its strictest sense, ROM refers only...
or ROM. Data and instructions were each addressed by separate 16-bit address bus
Address bus
An address bus is a computer bus that is used to specify a physical address. When a processor or DMA-enabled device needs to read or write to a memory location, it specifies that memory location on the address bus...
.
XAP2
A more powerful XAP2 was developed and used from 1999. It also had a Harvard architecture and 16-bit data, and it adopted a more conventional 16-bit instruction width suitable for program storage in FlashFlash memory
Flash memory is a non-volatile computer storage chip that can be electrically erased and reprogrammed. It was developed from EEPROM and must be erased in fairly large blocks before these can be rewritten with new data...
or other off-chip memories. Large programs were accommodated by a 24-bit address bus for instructions and there was a 16-bit address bus for data. XAP2 was a 12,000-gate processor with support for interrupts and a software tool chain including a C
C (programming language)
C is a general-purpose computer programming language developed between 1969 and 1973 by Dennis Ritchie at the Bell Telephone Laboratories for use with the Unix operating system....
compiler
Compiler
A compiler is a computer program that transforms source code written in a programming language into another computer language...
and the XAPASM assembler for its assembly language
Assembly language
An assembly language is a low-level programming language for computers, microprocessors, microcontrollers, and other programmable devices. It implements a symbolic representation of the machine codes and other constants needed to program a given CPU architecture...
. XAP2 was also used in Cambridge Consultants' ASIC designs and it was also provided to other semiconductor companies as a semiconductor intellectual property core
Semiconductor intellectual property core
In electronic design a semiconductor intellectual property core, IP core, or IP block is a reusable unit of logic, cell, or chip layout design that is the intellectual property of one party. IP cores may be licensed to another party or can be owned and used by a single party alone...
, or IP core.
XAP2 was adopted by three fabless semiconductor companies
Fabless semiconductor company
A fabless semiconductor company specializes in the design and sale of hardware devices and semiconductor chips while outsourcing the fabrication or "fab" of the devices to a specialized manufacturer called a semiconductor foundry...
that emerged from Cambridge Consultants: CSR plc
CSR plc
CSR , or Cambridge Silicon Radio, is a company based in Cambridge, England. CSR is a fabless semiconductor company whose main product lines include connectivity, audio and location chips. It is listed on the London Stock Exchange and is a constituent of the FTSE 250 Index...
(Cambridge Silicon Radio) is the main provider of Bluetooth chips for mobile phones and headsets; Ember Corporation is a leading supplier of ZigBee chips; and Cyan Technology supplies XAP2-powered microcontrollers. As a consequence, and combined with other licensees and Cambridge Consultants’ ASIC projects, there are now over one billion (1,000 million) XAP processors in use worldwide.
XAP3
XAP3 was designed at Cambridge Consultants in 2003 in response to a project requirement for a 32-bit processor. The project demanded a low cost and low energy ASIC implementation using modern CMOSCMOS
Complementary metal–oxide–semiconductor is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits...
semiconductor process technologies at 0.13 micrometre and below. This led Cambridge Consultants’ engineers to make certain design decisions including the use of a Von Neumann architecture
Von Neumann architecture
The term Von Neumann architecture, aka the Von Neumann model, derives from a computer architecture proposal by the mathematician and early computer scientist John von Neumann and others, dated June 30, 1945, entitled First Draft of a Report on the EDVAC...
, unified data and address bus, that enabled both the program's instructions and constants data to be held in a single on-chip memory. The program memory was to be either Flash
Flash memory
Flash memory is a non-volatile computer storage chip that can be electrically erased and reprogrammed. It was developed from EEPROM and must be erased in fairly large blocks before these can be rewritten with new data...
or one-time programmable EPROM
EPROM
An EPROM , or erasable programmable read only memory, is a type of memory chip that retains its data when its power supply is switched off. In other words, it is non-volatile. It is an array of floating-gate transistors individually programmed by an electronic device that supplies higher voltages...
and ASIC design is considerably simplified if a single memory is used without the need to pre-determine the split between instructions and fixed data. The XAP3's instruction set design also focussed on high code density to reduce the size of the program memory, thereby reducing cost and also the energy consumed by instruction fetches.
XAP4
In 2005, further project requirements saw a new 16-bit processor, the XAP4, designed to supersede the XAP2 taking into account the experience gained on XAP3 and the evolving requirements of ASIC designs. XAP4 is a very small, 12,000-gate, Von Neumann bus, 16-bit processor core capable of addressing a total of 64 kBytes of memory for programs, data and peripherals. It offers high code density combined with good performance in the region of 50 DhrystoneDhrystone
Dhrystone is a synthetic computing benchmark program developed in 1984 by Reinhold P. Weicker intended to be representative of system programming. The Dhrystone grew to become representative of general processor performance...
MIPS
Instructions per second
Instructions per second is a measure of a computer's processor speed. Many reported IPS values have represented "peak" execution rates on artificial instruction sequences with few branches, whereas realistic workloads typically lead to significantly lower IPS values...
when clocked at 80 MHz.
XAP4 was designed for use in modern ASIC or microcontroller
Microcontroller
A microcontroller is a small computer on a single integrated circuit containing a processor core, memory, and programmable input/output peripherals. Program memory in the form of NOR flash or OTP ROM is also often included on chip, as well as a typically small amount of RAM...
applications capable of processing real-world data captured by an Analog to digital converter (ADC) or similar sources. The processor's 16-bit integer word supports the precision of most ADCs without carrying the overhead of a 32-bit processor. XAP4 also offers a migration path from 8-bit processors, such as 8051
Intel 8051
The Intel MCS-51 is a Harvard architecture, single chip microcontroller series which was developed by Intel in 1980 for use in embedded systems. Intel's original versions were popular in the 1980s and early 1990s. While Intel no longer manufactures the MCS-51, binary compatible derivatives remain...
, in applications that need increased performance and program size, but cannot justify the cost and overhead of a 32-bit processor.
XAP5
Development of an extended version of this architecture commenced in 2006 and resulted in the XAP5, which was announced in July 2008. XAP5 is a 16-bit processor with a 24-bit address bus making it capable of running programs from memory up to 16 MBytes. XAP4 and XAP5 are both implemented with a two-stage instruction pipelineInstruction pipeline
An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput ....
, which maximises their performance when clocked at low frequencies. This is tailored to the requirements of small, low-energy ASICs as it minimises processor hardware size (the XAP5 core uses 18,000-gates), and it fits designs that are clocked relatively slowly to reduce an ASIC's dynamic power consumption and run programs direct from Flash or OTP memory that has a slow access time. Typical clock speeds for XAP5 are in the range of 16 to 100 MHz on a 0.13 process. XAP5 has particular design features making it suitable for executing programs from Flash including a Vector Pointer and an Address Translation Window, which combine to allow in-place execution of programs and relocation of programs regardless of where they are stored in physical memory.
Features
XAP3, XAP4 and XAP5 are all designed with a load-store RISC architecture that is complemented with multi-cycle instructions for multiplication, division, block copy/store and function entry/exit for maximum efficiency. Cambridge Consultants’ engineers recognised the requirement for these processors to run real-time operating systems capable of handling pre-emptive eventsPreemption (computing)
In computing, preemption is the act of temporarily interrupting a task being carried out by a computer system, without requiring its cooperation, and with the intention of resuming the task at a later time. Such a change is known as a context switch...
and with a fast interrupt
Interrupt
In computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution....
response. Consequently the processors are designed with hardware and instruction set support for protected software operating modes that partition user code from privileged operating system and interrupt handler code. The XAP processor hardware manages the mode transitions and call stack
Call stack
In computer science, a call stack is a stack data structure that stores information about the active subroutines of a computer program. This kind of stack is also known as an execution stack, control stack, run-time stack, or machine stack, and is often shortened to just "the stack"...
in response to events and this approach ensures a fast and deterministic interrupt response. The protected operating modes enable a system on a chip to be designed that is a secure or trustworthy system and offers high availability
High availability
High availability is a system design approach and associated service implementation that ensures a prearranged level of operational performance will be met during a contractual measurement period....
.
The current XAP processors are designed using the Verilog
Verilog
In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
hardware description language and provided as RTL
Register transfer level
In integrated circuit design, register-transfer level is a level of abstraction used in describing the operation of a synchronous digital circuit...
code ready for logic simulation
Logic simulation
Logic simulation is the use of a computer program to simulate the operation of a digital circuit. Logic simulation is the primary tool used for verifying the logical correctness of a hardware design. In many cases logic simulation is the first activity performed in the process of taking a hardware...
and logic synthesis
Logic synthesis
In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level , is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog...
with a test bench
Test bench
A test bench is a virtual environment used to verify the correctness or soundness of a design or model .The term has its roots in the testing of electronic devices, where an engineer would sit at a lab bench with tools for measurement and manipulation, such as oscilloscopes, multimeters, soldering...
. They are supported with Cambridge Consultants’ xIDE software development tools and SIF debug technology. These processors and tools enable functional verification
Functional verification
Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, and takes the...
and software verification
Software verification
Software verification is a broader and more complex discipline of software engineering whose goal is to assure that software fully satisfies all the expected requirements.There are two fundamental approaches to verification:...
that reduces the project risk, accelerates time-scales and cuts cost of ownership, especially for software engineering.