xman52
Hello friends,
Can anyone explain me the register renaming done in a 4 instuction window, how to do this renaming in verilog? If we are going for any renaming buffer, how to use that buffer for mapping and how this mapping is done?? If mapping is done, how to use this mapping in the write back stage of my CPU architecture, which has 7 stage pipeline like an Alpha processor 21264.
Can anyone explain me the register renaming done in a 4 instuction window, how to do this renaming in verilog? If we are going for any renaming buffer, how to use that buffer for mapping and how this mapping is done?? If mapping is done, how to use this mapping in the write back stage of my CPU architecture, which has 7 stage pipeline like an Alpha processor 21264.