Overview

Altos Design Automation, Inc. is an electronic design automation

Electronic design automation

Electronic design automation is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits...

software company. Altos develops and markets cell and semiconductor
intellectual property

Semiconductor intellectual property core

In electronic design a semiconductor intellectual property core, IP core, or IP block is a reusable unit of logic, cell, or chip layout design that is the intellectual property of one party. IP cores may be licensed to another party or can be owned and used by a single party alone...

 (IP) characterization tools that create library views
for timing, signal integrity

Signal integrity

Signal integrity or SI is a set of measures of the quality of an electrical signal. In digital electronics, a stream of binary values is represented by a voltage waveform. However, digital signals are fundamentally analog in nature, and all signals are subject to effects such as noise,...

 and power analysis and optimization.The Altos
tools are fully automated and the company claims that its tools are
extremely fast. The Altos tools are used by engineers employing both
corner-based and statistical-based design implementation flows to reduce
time-to -market and improve yield.

Altos is privately held and was founded in January 2005 in Santa Clara,
California by former employees of Cadence Design Systems. All members of the
team worked at CadMOS where they were responsible for the development of
Signal Integrity analysis tools for both cell- and transistor-level digital
IC designers.

Its corporate headquarters is in San Jose, California.

Products

Variety
Variety creates statistical timing cell models that represent the non-linear impact of any number of systematic and random parameter variations. All library timing data is characterized for variation including delays, transitions, timing constraints, and pin capacitances. Variety generates statistical static timing analysis

Statistical static timing analysis

Conventional static timing analysis has been a stock analysis algorithm for the design of digital circuits over the last 30 years. However, in recent years the increased variation in semiconductor devices and interconnect has introduced a number of issues that cannot be handled by traditional STA...

 (SSTA) models for a number of commercial SSTA products from a single characterization run.

Liberate
Liberate is an automated library characterization tool for standard cells and I/Os that serves existing static timing analyzers

Static timing analysis

Static Timing Analysis is a method of computing the expected timing of a digital circuit without requiring simulation.High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate...

. Liberate takes in a Spice netlist and Spice subcircuits, and automatically generates a characterized cell library. It supports both Composite Current Source (CCS) model backed by Synopsys and the Effective Current Source Model (ECSM) backed by Cadence Design Systems.