Amber (processor core)
Encyclopedia
The Amber processor core is an Open-source ARM
-compatible 32-bit RISC processor. It is hosted on the OpenCores
website and is part of a movement to develop a library of open source hardware intellectual property. The Amber core is fully compatible with the ARMv2 instruction set
and is therefore supported by the GNU toolchain
. This older version of the ARM instruction set is supported because it is not covered by patents so can be implemented without a license from ARM Holdings
, unlike some previous open source projects. The Amber project provides a complete embedded FPGA
system incorporating the Amber core and a number of peripherals, including UARTs, timers and an Ethernet
MAC.
There are two versions of the core provided in the Amber project. The Amber 23 has a 3-stage pipeline, a unified instruction and data cache, a Wishbone interface, and is capable of 0.75 DMIPS per MHz. The Amber 25 has a 5-stage pipeline, separate data and instruction caches, a Wishbone interface, and is capable of 1.0 DMIPS per MHz. Both cores implement exactly the same ISA and are 100% software compatible.
The Amber 23 core is a very small 32-bit core that provides good performance. Register-based instructions execute in a single cycle, except for instructions involving multiplication. Load and store instructions require three cycles. The core's pipeline is stalled either when a cache miss occurs, or when the core performs a wishbone access.
The Amber 25 core provides 30 to 40% better performance than the Amber 23 core but is also 30 to 40% larger. Register-based instructions execute in a single cycle, except for instructions involving multiplication, or complex shift operations. Load and store
instructions also execute in a single cycle unless there is a register conflict with a following instruction. The core's pipeline is stalled when a cache miss occurs in either cache, when an instruction conflict is detected, when a complex shift is executed, or when the core performs a wishbone access.
Both cores has been verified by booting a Linux
2.4 kernel. Versions of the Linux kernel
from the 2.4 branch and earlier contain configurations for the supported ISA. The 2.6 and later versions of the Linux kernel do not explicitly support the ARM v2a ISA and so requires more modifications to run. The cores do not contain a memory management unit
(MMU) so they can only run the non-virtual memory variant of Linux, μClinux.
The cores were developed in Verilog
2001, and are optimized for FPGA
synthesis. For example there is no reset logic, all registers are reset as part of FPGA initialization.
For a description of the ARMv2 ISA, see Archimedes Operating System - A Dabhand Guide, or Acorn RISC Machine Family Data Manual.
ARM architecture
ARM is a 32-bit reduced instruction set computer instruction set architecture developed by ARM Holdings. It was named the Advanced RISC Machine, and before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in numbers produced...
-compatible 32-bit RISC processor. It is hosted on the OpenCores
OpenCores
OpenCores is the world's largest open source hardware community developing digital open source hardware through electronic design automation, with a similar ethos to the free software movement. OpenCores hopes to eliminate redundant design work and slash development costs. A number of companies...
website and is part of a movement to develop a library of open source hardware intellectual property. The Amber core is fully compatible with the ARMv2 instruction set
Instruction set
An instruction set, or instruction set architecture , is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O...
and is therefore supported by the GNU toolchain
GNU toolchain
The GNU toolchain is a blanket term for a collection of programming tools produced by the GNU Project. These tools form a toolchain used for developing applications and operating systems....
. This older version of the ARM instruction set is supported because it is not covered by patents so can be implemented without a license from ARM Holdings
ARM Holdings
ARM Holdings plc is a British multinational semiconductor and software company headquartered in Cambridge. Its largest business is in processors, although it also designs, licenses and sells software development tools under the RealView and KEIL brands, systems and platforms, system-on-a-chip...
, unlike some previous open source projects. The Amber project provides a complete embedded FPGA
Field-programmable gate array
A field-programmable gate array is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable"...
system incorporating the Amber core and a number of peripherals, including UARTs, timers and an Ethernet
Ethernet
Ethernet is a family of computer networking technologies for local area networks commercially introduced in 1980. Standardized in IEEE 802.3, Ethernet has largely replaced competing wired LAN technologies....
MAC.
There are two versions of the core provided in the Amber project. The Amber 23 has a 3-stage pipeline, a unified instruction and data cache, a Wishbone interface, and is capable of 0.75 DMIPS per MHz. The Amber 25 has a 5-stage pipeline, separate data and instruction caches, a Wishbone interface, and is capable of 1.0 DMIPS per MHz. Both cores implement exactly the same ISA and are 100% software compatible.
The Amber 23 core is a very small 32-bit core that provides good performance. Register-based instructions execute in a single cycle, except for instructions involving multiplication. Load and store instructions require three cycles. The core's pipeline is stalled either when a cache miss occurs, or when the core performs a wishbone access.
The Amber 25 core provides 30 to 40% better performance than the Amber 23 core but is also 30 to 40% larger. Register-based instructions execute in a single cycle, except for instructions involving multiplication, or complex shift operations. Load and store
instructions also execute in a single cycle unless there is a register conflict with a following instruction. The core's pipeline is stalled when a cache miss occurs in either cache, when an instruction conflict is detected, when a complex shift is executed, or when the core performs a wishbone access.
Both cores has been verified by booting a Linux
Linux
Linux is a Unix-like computer operating system assembled under the model of free and open source software development and distribution. The defining component of any Linux system is the Linux kernel, an operating system kernel first released October 5, 1991 by Linus Torvalds...
2.4 kernel. Versions of the Linux kernel
Linux kernel
The Linux kernel is an operating system kernel used by the Linux family of Unix-like operating systems. It is one of the most prominent examples of free and open source software....
from the 2.4 branch and earlier contain configurations for the supported ISA. The 2.6 and later versions of the Linux kernel do not explicitly support the ARM v2a ISA and so requires more modifications to run. The cores do not contain a memory management unit
Memory management unit
A memory management unit , sometimes called paged memory management unit , is a computer hardware component responsible for handling accesses to memory requested by the CPU...
(MMU) so they can only run the non-virtual memory variant of Linux, μClinux.
The cores were developed in Verilog
Verilog
In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
2001, and are optimized for FPGA
Field-programmable gate array
A field-programmable gate array is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable"...
synthesis. For example there is no reset logic, all registers are reset as part of FPGA initialization.
For a description of the ARMv2 ISA, see Archimedes Operating System - A Dabhand Guide, or Acorn RISC Machine Family Data Manual.