Answer to reset
Encyclopedia
An Answer To Reset is a message output by a contact Smart Card
conforming to ISO/IEC 7816 standards, following electrical reset of the card's chip by a card reader. The ATR conveys information about the communication parameters proposed by the card, and the card's nature and state.
By extension, ATR often refers to a message obtained from a Smart Card in an early communication stage; or from the card reader used to access that card, which may transform the card's message into an ATR-like format (this occurs e.g. for some PC/SC
card readers when accessing an ISO/IEC 14443 Smart Card).
The presence of an ATR is often used as a first indication that a Smart Card appears operative, and its content examined as a first test that it is of the appropriate kind for a given usage.
Contact Smart Cards communicate over a signal named Input/Output (I/O) either synchronously (data bits are sent and received at the rhythm of one per period of the clock supplied to the card on its CLK signal) or asynchronously (data bits are exchanged over I/O with another mechanism for bit delimitation, similar to traditional asynchronous serial communication). The two modes are exclusive in a given communication session, and most cards are built with support for a single mode. Microprocessor-based contact Smart Cards are mostly of the asynchronous variety, used for all Subscriber Identity Module
s (SIM) for mobile phones, all bank card
s with contacts conforming to EMV
specifications, all contact Java Card
s, and Smart Cards for pay television. Memory-only cards are generally of the synchronous variety.
ATR under asynchronous and synchronous transmission have entirely different form and content. The ATR in asynchronous transmission is extensively normalized, and relatively complex to parse.
Some Smart Cards (mostly of the asynchronous variety) have different ATR depending on if the reset is the first since power-up (Cold ATR) or not (Warm ATR).
Note: Answer To Reset should not be confused with ATtRibute REQuest (ATR_REQ) and ATtRibute RESponse (ATR_RES) of NFC
, also abbreviated ATR. ATR_RES conveys information about the communication parameters supported, as does Answer To Reset, but its structure is different.
.
The ATR proceeds in five steps: initial character TS; format byte T0; interface bytes TAi, TBi, TCi, TDi (optionals, variable number); historical bytes Ti (optionals, up to 15), and the check byte TCK (optional). There are a total of 2 to 33 characters including TS.
The initial character TS is always physically present, but is not part of the Answer-to-Reset in ISO/IEC 7816-3:2006, defined as: the value of the byte string (at most 32 bytes) encoded in the sequence of characters following the initial character TS. ISO/IEC 7816-4:2005 states that TS is a character or synchronization pattern, not a byte]. However practice (in PC/SC
, EMV
, ETSI, and Calypso at least) is still to consider that TS is part of the ATR, as it was in ISO/IEC 7816-3:1997 and former. In particular, the ATR returned by PC/SC card readers and software stacks includes TS as the first byte, with the value explicitly given in every edition of ISO/IEC 7816-3, see below.
of each data byte is first (resp. last) in the physical transmission by the card.
For direct convention, TS is (H) L H H L H H H L L H (H) and encodes the byte ‘3B’.
For inverse convention, TS is (H) L H H L L L L L L H (H) and encodes the byte ‘3F’.
[ (H) represents the idle (High, Mark) state of the I/O line. The 8 data bits are shown in italic.]
In the following bytes of the ATR, bits are numbered 1st to 8th from low-order to high-order, and their value noted 0 or 1, regardless of the chronological order and electrical representation, defined by TS.
TS also allows the card reader to confirm or determine the duration of bits, denoted Elementary Time Unit (ETU), as one third of the delay between the first and second H-to-L transition in TS. This is optional, and the principal definition of ETU in the ATR of standard-compliant asynchronous Smart Cards is 372 periods of the clock received by the card.
Historical note: provision for cards that use an internal clock source and a fixed ETU of 1/9600 second during ATR existed in ISO/IEC 7816-3:1989, and was removed from the 1997 edition onwards.
It also encodes in its 4 high-order bits the presence of at most 4 other interface bytes: TA1 (resp. TB1, TC1, TD1) follow, in that order, if the 5th (resp. 6th, 7th, 8th) bit of T0 is 1.
Interface bytes come in three kinds: global interface bytes apply to all protocols; specific interface bytes apply to a specific protocol; and structural interface bytes introduce further interface bytes, and protocols.
The 4 low-order bits of TA1 encode Di as:
(#) This was RFU in ISO/IEC 7816-3:1997 and former. Some card readers or drivers may erroneously reject cards using this value (or other RFU).
The 4 high-order bits of TA1 encode fmax and Fi as:
(#) Historical note: in ISO/IEC 7816-3:1989, this was assigned to cards with internal clock, and thus no assigned Fi or f(max).
For example, TA1 = 'B5' = 10110101 encodes fmax = 10 MHz, Fi/Di = 1024/16 = 64; this is inviting the card reader to take (after the ATR) the necessary steps to reduce the ETU to 64 clock cycles per ETU (from 372 during ATR) and increase the clock frequency up to 10 MHz (from perhaps 4 MHz during ATR).
memory. Modern Smart Cards internally generate the programming voltage for their EEPROM
or Flash
memory, and the usage of TB1 is deprecated since the 2006 edition of the standard. Nowadays, cards should not include it in the ATR, and readers shall ignore TB1 if present. Including TB1='00' (indicating that the card does not use VPP) remains common.
In the 1997 and earlier editions of the standard:
- The low 5 bits of TB1 (5th to 1st) encode PI1; if TB2 is absent, PI1=0 indicates that the C6 contact (assigned to VPP) is not connected in the card; PI1 in range [5..25] encodes the value of VPP in Volt (the reader shall apply that voltage only on specific demand by the card, with a tolerance of 2.5%, up to the maximum programming current; and otherwise leave the C6 contact used for VPP within 5% of the VCC voltage, up to 20 mA); if TB2 is present, it supersedes the indication given by TB1 in the PI1 field, regarding VPP connection or voltage.
- The high bit of TB1 (8th bits) is reserved, shall be 0, and can be ignored by the reader.
- The 6th and 5th bits of TB1 encode the maximum programming current (assuming neither TB1 nor TB2 indicate that VPP is not connected in the card)
(#) This was 100 mA in ISO/IEC 7816-3:1989.
TDi encodes in its 4 high-order bits the presence of at most 4 other interface bytes: TAi+1 (resp. TBi+1, TCi+1, TDi+1) follow, in that order, if the 5th (resp. 6th, 7th, 8th) bit of TDi is 1.
TDi encodes in its 4 low-order bits an integer T, which is in range [0..15]. T=15 qualifies the following TAi+1 TBi+1, TCi+1, TDi+1 (if present) as global interface bytes. Otherwise, T indicates a protocol that the card is willing to use, and that TAi+1 TBi+1, TCi+1, TDi+1 (if present) are specific interface bytes applying only to that protocol. T=0 is a character-oriented protocol. T=1 is a block-oriented protocol. T in the range [3..14] is RFU.
Historical note: provision for dynamically qualifying interface bytes as global using T=15 did not exist in ISO/IEC 7816-3:1989.
Presence of TA2 globally (hence the kind) commands that the reader use specific mode (hence the name) as defined by TA2 and earlier global bytes, rather than negotiable mode when TA2 is absent.
Historical note: Provision for specific mode did not exist in ISO/IEC 7816-3:1989. Back then, the interface character TA2 had no particular name or function, and was specific (to the protocol introduced by TD1). ISO/IEC 7816-3:1997 introduced the specific mode and the specific mode byte, with interim note helping cards with specific mode byte TA2 in their ATR dealing with a reader that did not implement specific mode.
Presence of TCK is determined by the values of T which may be encoded in some Interface bytes.
The ATR starts with a header of 32 bits organized into 4 bytes, denoted H1 thru H4. H1 codes the protocol (with '00' and 'FF' being invalid), H2 codes parameters of the protocol. Little more is standardized.
Smart card
A smart card, chip card, or integrated circuit card , is any pocket-sized card with embedded integrated circuits. A smart card or microprocessor cards contain volatile memory and microprocessor components. The card is made of plastic, generally polyvinyl chloride, but sometimes acrylonitrile...
conforming to ISO/IEC 7816 standards, following electrical reset of the card's chip by a card reader. The ATR conveys information about the communication parameters proposed by the card, and the card's nature and state.
By extension, ATR often refers to a message obtained from a Smart Card in an early communication stage; or from the card reader used to access that card, which may transform the card's message into an ATR-like format (this occurs e.g. for some PC/SC
PC/SC
PC/SC is a specification for smart-card integration into computing environments.Microsoft has implemented PC/SC in Microsoft Windows 200x/XP and makes it available under Microsoft Windows NT/9x....
card readers when accessing an ISO/IEC 14443 Smart Card).
The presence of an ATR is often used as a first indication that a Smart Card appears operative, and its content examined as a first test that it is of the appropriate kind for a given usage.
Contact Smart Cards communicate over a signal named Input/Output (I/O) either synchronously (data bits are sent and received at the rhythm of one per period of the clock supplied to the card on its CLK signal) or asynchronously (data bits are exchanged over I/O with another mechanism for bit delimitation, similar to traditional asynchronous serial communication). The two modes are exclusive in a given communication session, and most cards are built with support for a single mode. Microprocessor-based contact Smart Cards are mostly of the asynchronous variety, used for all Subscriber Identity Module
Subscriber Identity Module
A subscriber identity module or subscriber identification module is an integrated circuit that securely stores the International Mobile Subscriber Identity and the related key used to identify and authenticate subscriber on mobile telephony devices .A SIM is held on a removable SIM card, which...
s (SIM) for mobile phones, all bank card
Bank card
A bank card is a plastic card issued by a bank to its clients that may perform one or more of the following services:* ATM card, card used for transactions at automatic teller machines* Debit card, card linked to a bank account and used for making purchases...
s with contacts conforming to EMV
EMV
EMV stands for Europay, MasterCard and VISA, a global standard for inter-operation of integrated circuit cards and IC card capable point of sale terminals and automated teller machines , for authenticating credit and debit card transactions.It is a joint effort between Europay, MasterCard and...
specifications, all contact Java Card
Java Card
Java Card refers to a technology that allows Java-dd applications to be run securely on smart cards and similar small memory footprint devices. Java Card is the tiniest of Java targeted for embedded devices. Java Card gives the user ability to program the device and make them application...
s, and Smart Cards for pay television. Memory-only cards are generally of the synchronous variety.
ATR under asynchronous and synchronous transmission have entirely different form and content. The ATR in asynchronous transmission is extensively normalized, and relatively complex to parse.
Some Smart Cards (mostly of the asynchronous variety) have different ATR depending on if the reset is the first since power-up (Cold ATR) or not (Warm ATR).
Note: Answer To Reset should not be confused with ATtRibute REQuest (ATR_REQ) and ATtRibute RESponse (ATR_RES) of NFC
NFC
NFC may refer to:* Nagacorp FC, a Cambodian sporting club* National Finance Center, a division of the United States Department of Agriculture* National Football Conference, a constituent conference of the National Football League...
, also abbreviated ATR. ATR_RES conveys information about the communication parameters supported, as does Answer To Reset, but its structure is different.
ATR in asynchronous transmission
The standard defining the ATR in asynchronous transmission is ISO/IEC 7816-3. Subsets of the full ATR specification are used for some Smart Card applications, e.g. EMVEMV
EMV stands for Europay, MasterCard and VISA, a global standard for inter-operation of integrated circuit cards and IC card capable point of sale terminals and automated teller machines , for authenticating credit and debit card transactions.It is a joint effort between Europay, MasterCard and...
.
The ATR proceeds in five steps: initial character TS; format byte T0; interface bytes TAi, TBi, TCi, TDi (optionals, variable number); historical bytes Ti (optionals, up to 15), and the check byte TCK (optional). There are a total of 2 to 33 characters including TS.
The initial character TS is always physically present, but is not part of the Answer-to-Reset in ISO/IEC 7816-3:2006, defined as: the value of the byte string (at most 32 bytes) encoded in the sequence of characters following the initial character TS. ISO/IEC 7816-4:2005 states that TS is a character or synchronization pattern, not a byte]. However practice (in PC/SC
PC/SC
PC/SC is a specification for smart-card integration into computing environments.Microsoft has implemented PC/SC in Microsoft Windows 200x/XP and makes it available under Microsoft Windows NT/9x....
, EMV
EMV
EMV stands for Europay, MasterCard and VISA, a global standard for inter-operation of integrated circuit cards and IC card capable point of sale terminals and automated teller machines , for authenticating credit and debit card transactions.It is a joint effort between Europay, MasterCard and...
, ETSI, and Calypso at least) is still to consider that TS is part of the ATR, as it was in ISO/IEC 7816-3:1997 and former. In particular, the ATR returned by PC/SC card readers and software stacks includes TS as the first byte, with the value explicitly given in every edition of ISO/IEC 7816-3, see below.
Initial character TS
The initial character TS encodes the convention used for encoding of the ATR (and further communications until the next reset). In direct [resp. inverse] convention, bits with logic value ‘1’ are transferred as a High voltage (H) [resp. a Low voltage (L)]; bits with logic value ‘0’ are transferred as L [resp. H]; and least-significant bitLeast significant bit
In computing, the least significant bit is the bit position in a binary integer giving the units value, that is, determining whether the number is even or odd. The lsb is sometimes referred to as the right-most bit, due to the convention in positional notation of writing less significant digits...
of each data byte is first (resp. last) in the physical transmission by the card.
For direct convention, TS is (H) L H H L H H H L L H (H) and encodes the byte ‘3B’.
For inverse convention, TS is (H) L H H L L L L L L H (H) and encodes the byte ‘3F’.
[ (H) represents the idle (High, Mark) state of the I/O line. The 8 data bits are shown in italic.]
In the following bytes of the ATR, bits are numbered 1st to 8th from low-order to high-order, and their value noted 0 or 1, regardless of the chronological order and electrical representation, defined by TS.
TS also allows the card reader to confirm or determine the duration of bits, denoted Elementary Time Unit (ETU), as one third of the delay between the first and second H-to-L transition in TS. This is optional, and the principal definition of ETU in the ATR of standard-compliant asynchronous Smart Cards is 372 periods of the clock received by the card.
Historical note: provision for cards that use an internal clock source and a fixed ETU of 1/9600 second during ATR existed in ISO/IEC 7816-3:1989, and was removed from the 1997 edition onwards.
Format byte T0
The Format byte T0 encodes in its 4 low-order bits the number Y of historical bytes, in range [0..15].It also encodes in its 4 high-order bits the presence of at most 4 other interface bytes: TA1 (resp. TB1, TC1, TD1) follow, in that order, if the 5th (resp. 6th, 7th, 8th) bit of T0 is 1.
Interface bytes TAi, TBi, TCi, TDi
Interface bytes TA1, TB1, TC1, TD1, TA2, TB2, TC2, TD2, TA3, TB3, .. are all optional, and encode communication parameters and protocols that the card propose to use.Interface bytes come in three kinds: global interface bytes apply to all protocols; specific interface bytes apply to a specific protocol; and structural interface bytes introduce further interface bytes, and protocols.
Interface byte TA1
Interface byte TA1, if present, is global. It encodes the maximum clock frequency fmax supported by the card, and the number of clock periods per ETU that it suggests to use after the ATR, expressed as the ratio Fi/Di of two integers.The 4 low-order bits of TA1 encode Di as:
| 4th to 1st bits | 0000 | 0001 | 0010 | 0011 | 0100 | 0101 | 0110 | 0111 | 1000 | 1001 | 1010 | 1011 | 1100 | 1101 | 1110 | 1111 |
| Di | RFU | 1 | 2 | 4 | 8 | 16 | 32 | 64(#) | 12 | 20 | RFU | RFU | RFU | RFU | RFU | RFU |
The 4 high-order bits of TA1 encode fmax and Fi as:
| 8th to 5th bits | 0000 | 0001 | 0010 | 0011 | 0100 | 0101 | 0110 | 0111 | 1000 | 1001 | 1010 | 1011 | 1100 | 1101 | 1110 | 1111 |
| Fi | 372(#) | 372 | 558 | 744 | 1116 | 1488 | 1860 | RFU | RFU | 512 | 768 | 1024 | 1536 | 2048 | RFU | RFU |
| fmax (MHz) | 4(#) | 5 | 6 | 8 | 12 | 16 | 20 | — | — | 5 | 7.5 | 10 | 15 | 20 | — | — |
For example, TA1 = 'B5' = 10110101 encodes fmax = 10 MHz, Fi/Di = 1024/16 = 64; this is inviting the card reader to take (after the ATR) the necessary steps to reduce the ETU to 64 clock cycles per ETU (from 372 during ATR) and increase the clock frequency up to 10 MHz (from perhaps 4 MHz during ATR).
Interface byte TB1
TB1, if present, is global. It used to indicate the programming voltage VPP and maximum programming current required by some cards on the dedicated contact C6 during programming of their EPROMEPROM
An EPROM , or erasable programmable read only memory, is a type of memory chip that retains its data when its power supply is switched off. In other words, it is non-volatile. It is an array of floating-gate transistors individually programmed by an electronic device that supplies higher voltages...
memory. Modern Smart Cards internally generate the programming voltage for their EEPROM
EEPROM
EEPROM stands for Electrically Erasable Programmable Read-Only Memory and is a type of non-volatile memory used in computers and other electronic devices to store small amounts of data that must be saved when power is removed, e.g., calibration...
or Flash
Flash memory
Flash memory is a non-volatile computer storage chip that can be electrically erased and reprogrammed. It was developed from EEPROM and must be erased in fairly large blocks before these can be rewritten with new data...
memory, and the usage of TB1 is deprecated since the 2006 edition of the standard. Nowadays, cards should not include it in the ATR, and readers shall ignore TB1 if present. Including TB1='00' (indicating that the card does not use VPP) remains common.
In the 1997 and earlier editions of the standard:
- The low 5 bits of TB1 (5th to 1st) encode PI1; if TB2 is absent, PI1=0 indicates that the C6 contact (assigned to VPP) is not connected in the card; PI1 in range [5..25] encodes the value of VPP in Volt (the reader shall apply that voltage only on specific demand by the card, with a tolerance of 2.5%, up to the maximum programming current; and otherwise leave the C6 contact used for VPP within 5% of the VCC voltage, up to 20 mA); if TB2 is present, it supersedes the indication given by TB1 in the PI1 field, regarding VPP connection or voltage.
- The high bit of TB1 (8th bits) is reserved, shall be 0, and can be ignored by the reader.
- The 6th and 5th bits of TB1 encode the maximum programming current (assuming neither TB1 nor TB2 indicate that VPP is not connected in the card)
| 7th and 6th bits | 00 | 01 | 10 | 11 |
| Maximum programming current | 25 mA | 50 mA | RFU(#) | RFU |
Interface byte TC1
TC1 encodes the extra guard time integer (N) from 0 to 255 over the eight bits. The default value is N = 0.Interface bytes TDi
Interface byte TDi for i>0, if present, is structural.TDi encodes in its 4 high-order bits the presence of at most 4 other interface bytes: TAi+1 (resp. TBi+1, TCi+1, TDi+1) follow, in that order, if the 5th (resp. 6th, 7th, 8th) bit of TDi is 1.
TDi encodes in its 4 low-order bits an integer T, which is in range [0..15]. T=15 qualifies the following TAi+1 TBi+1, TCi+1, TDi+1 (if present) as global interface bytes. Otherwise, T indicates a protocol that the card is willing to use, and that TAi+1 TBi+1, TCi+1, TDi+1 (if present) are specific interface bytes applying only to that protocol. T=0 is a character-oriented protocol. T=1 is a block-oriented protocol. T in the range [3..14] is RFU.
Historical note: provision for dynamically qualifying interface bytes as global using T=15 did not exist in ISO/IEC 7816-3:1989.
Interface byte TA2
Interface byte TA2, if present, is global, and is named the specific mode byte.Presence of TA2 globally (hence the kind) commands that the reader use specific mode (hence the name) as defined by TA2 and earlier global bytes, rather than negotiable mode when TA2 is absent.
Historical note: Provision for specific mode did not exist in ISO/IEC 7816-3:1989. Back then, the interface character TA2 had no particular name or function, and was specific (to the protocol introduced by TD1). ISO/IEC 7816-3:1997 introduced the specific mode and the specific mode byte, with interim note helping cards with specific mode byte TA2 in their ATR dealing with a reader that did not implement specific mode.
Historical bytes Ti
Historical Characters typically hold Information about the Card Builder, Type of Card (Size etc.), Version number and the State of the Card.Check byte TCK
The Check byte adds redundancy to the ATR. If present, it is the Exclusive OR of the bytes in the ATR from T0 to the byte before TCK, included.Presence of TCK is determined by the values of T which may be encoded in some Interface bytes.
ATR in synchronous transmission
The official reference defining the ATR in synchronous transmission is the ISO/IEC 7816-10 standard.The ATR starts with a header of 32 bits organized into 4 bytes, denoted H1 thru H4. H1 codes the protocol (with '00' and 'FF' being invalid), H2 codes parameters of the protocol. Little more is standardized.