In computing, cache coherence (also cache coherency) refers to the consistency of data stored in local cache

Cache

In computer engineering, a cache is a component that transparently stores data so that future requests for that data can be served faster. The data that is stored within a cache might be values that have been computed earlier or duplicates of original values that are stored elsewhere...

s of a shared resource.

When clients in a system maintain caches

CPU cache

A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations...

 of a common memory resource, problems may arise with inconsistent data. This is particularly true of CPUs in a multiprocessing

Multiprocessing

Multiprocessing is the use of two or more central processing units within a single computer system. The term also refers to the ability of a system to support more than one processor and/or the ability to allocate tasks between them...

 system. Referring to the "Multiple Caches of Shared Resource" figure, if the top client has a copy of a memory block from a previous read and the bottom client changes that memory block, the top client could be left with an invalid cache of memory without any notification of the change. Cache coherence is intended to manage such conflicts and maintain consistency between cache and memory.

Coherency protocol

A coherency protocol is a protocol which maintains the consistency between all the caches in a system of distributed shared memory

Distributed shared memory

Distributed Shared Memory , in Computer Architecture is a form of memory architecture where the memories can be addressed as one address space...

. The protocol maintains memory coherence

Memory coherence

Memory coherence is an issue that affects the design of computer systems in which two or more processors or cores share a common area of memory....

 according to a specific consistency model

Consistency model

In computer science, consistency models are used in distributed systems like distributed shared memory systems or distributed data stores . The system supports a given model, if operations on memory follow specific rules...

. Older multiprocessors support the sequential consistency

Sequential consistency

Sequential consistency is one of the consistency models used in the domain of concurrent programming . It was first defined as the property that requires that ".....

 model, while modern shared memory systems typically support the release consistency

Release consistency

Release consistency is one of the consistency models used in the domain of the concurrent programming ....

 or weak consistency

Weak consistency

The name weak consistency may be used in two senses. In the first sense, strict and more popular, the weak consistency is one of the consistency models used in the domain of the concurrent programming The name weak consistency may be used in two senses. In the first sense, strict and more popular,...

 models.

Transitions between states in any specific implementation of these protocols may vary. For example, an implementation may choose different update and invalidation transitions such as update-on-read, update-on-write, invalidate-on-read, or invalidate-on-write. The choice of transition may affect the amount of inter-cache traffic, which in turn may affect the amount of cache bandwidth available for actual work. This should be taken into consideration in the design of distributed software that could cause strong contention between the caches of multiple processors.

Various models and protocols have been devised for maintaining cache coherence, such as MSI protocol

MSI protocol

The MSI protocol is a basic Cache coherence protocol that is used in multiprocessor systems. As with other cache coherency protocols, the letters of the protocol name identify the possible states in which a cache line can be. So, for MSI, each block contained inside a cache can have one of three...

, MESI

MESI protocol

The MESI protocol is a widely used cache coherency and memory coherence protocol. It is the most common protocol which supports write-back cache...

 (aka Illinois protocol), MOSI

MOSI protocol

The MOSI protocol is an extension of the basic MSI cache coherency protocol. It adds the Owned state, which indicates that the current processor owns this block, and will service requests from other processors for the block....

, MOESI

MOESI protocol

In computing, MOESI is a full cache coherency protocol that encompasses all of the possible states commonly used in other protocols. In addition to the four common MESI protocol states, there is a fifth "Owned" state representing data that is both modified and shared. This avoids the need to...

, MERSI

MERSI protocol

The MERSI protocol is a cache coherency and memory coherence protocol used by the PowerPC G4. The protocol consists of five states, Modified , Exclusive , Read Only or Recent , Shared and Invalid . The M, E, S and I states are the same as in the MESI protocol...

, MESIF

MESIF protocol

The MESIF protocol is a cache coherency and memory coherence protocol developed by Intel for cache coherent non-uniform memory architectures. The protocol consists of five states, Modified , Exclusive , Shared , Invalid and Forward ....

, write-once, Synapse, Berkeley, Firefly

Firefly protocol

The Firefly cache coherence protocol is the schema used in the DEC Firefly multiprocessor workstation, developed by DEC Systems Research Center. This protocol uses a write-through policy.- States :...

 and Dragon protocol

Dragon protocol

The Dragon cache coherence protocol is the schema used in the Xerox Dragon multiprocessor workstation, developed by Xerox PARC. This protocol uses a write-back policy.- States :In this protocol, the following states can be assigned to each block:...

Choice of the consistency model

Consistency model

In computer science, consistency models are used in distributed systems like distributed shared memory systems or distributed data stores . The system supports a given model, if operations on memory follow specific rules...

 is crucial to designing a cache coherent system. Coherence models differ in performance and scalability; each must be evaluated for every system design.

See also

• ccNUMA
• Memory barrier
  Memory barrier
  Memory barrier, also known as membar or memory fence or fence instruction, is a type of barrier and a class of instruction which causes a central processing unit or compiler to enforce an ordering constraint on memory operations issued before and after the barrier instruction.CPUs employ...