Core Multiplexing Technology
Encyclopedia
Core Multiplexing Technology is a term that appeared in some BIOS
es; some people believe that it is an implementation of speculative multithreading
technology developed by Intel, previously known as Core Mitosis to allow for multicore CPUs to act as a single, more powerful CPU core.
Much in the same way a branch predictor
allows for a processor to speculate on the outcome of a branch operation without actually performing the operation, speculative multithreading allows for the processor to speculate deeper, executing entire branches of code on an additional core. Most of the implementation is done in software, with the compiler rearranging code to take better use of a multithreaded platform, which allows SMT
and Multicore
systems (or a combination of the two) to take advantage of the technology. But, because the data dependencies of speculative multithreading, and the necessity to manage inter-thread dependent data, hardware
implementation must be taken into consideration.
Core Multiplexing Technology is thought to leverage Intel's Advanced Smart Cache technology of the upcoming Core 2 chips, which allows two cores to share a single L2 cache, and actively resize the cache between the two processors if one is idle, by allowing the two cores to share data to manage inter-thread dependent data.
BIOS
In IBM PC compatible computers, the basic input/output system , also known as the System BIOS or ROM BIOS , is a de facto standard defining a firmware interface....
es; some people believe that it is an implementation of speculative multithreading
Speculative multithreading
Speculative multithreading , also known as thread level speculation , is a dynamic parallelization technique that depends on out-of-order execution to achieve speedup on multiprocessor CPUs. It is a kind of speculative execution that occurs at the thread level as opposed to the instruction level....
technology developed by Intel, previously known as Core Mitosis to allow for multicore CPUs to act as a single, more powerful CPU core.
Details
A subset of traditional applications are often difficult to parallelize and make use of additional CPU hardware available on the platform, restraining applications to use only one CPU. Corey the introduction of speculative multithreading.Much in the same way a branch predictor
Branch predictor
In computer architecture, a branch predictor is a digital circuit that tries to guess which way a branch will go before this is known for sure. The purpose of the branch predictor is to improve the flow in the instruction pipeline...
allows for a processor to speculate on the outcome of a branch operation without actually performing the operation, speculative multithreading allows for the processor to speculate deeper, executing entire branches of code on an additional core. Most of the implementation is done in software, with the compiler rearranging code to take better use of a multithreaded platform, which allows SMT
SMT
SMT may refer to:* Satisfiability Modulo Theories* Statistical machine translation* Scottish Mortgage Investment Trust PLC * Scottish Motor Traction, a former bus company in Scotland...
and Multicore
Multicore
Multicore may refer to:* Multi-core processor ** Multicore Association, founded in 2005, a non-profit, industry consortium focused on multicore technology* multicore cable, a generic term for an electrical cable that has multiple cores...
systems (or a combination of the two) to take advantage of the technology. But, because the data dependencies of speculative multithreading, and the necessity to manage inter-thread dependent data, hardware
Hardware
Hardware is a general term for equipment such as keys, locks, hinges, latches, handles, wire, chains, plumbing supplies, tools, utensils, cutlery and machine parts. Household hardware is typically sold in hardware stores....
implementation must be taken into consideration.
Core Multiplexing Technology is thought to leverage Intel's Advanced Smart Cache technology of the upcoming Core 2 chips, which allows two cores to share a single L2 cache, and actively resize the cache between the two processors if one is idle, by allowing the two cores to share data to manage inter-thread dependent data.