DEC Firefly
Encyclopedia
The Firefly was a shared memory
asymmetric multiprocessor workstation
, developed by the Systems Research Center
, a research organization within Digital Equipment Corporation
. The first version built contained up to seven MicroVAX 78032
microprocessors. The cache from each of the microprocessors kept a consistent view of the same main memory using a cache coherency
algorithm, the Firefly protocol
. The second version of the Firefly used faster CVAX 78034 microprocessors.
interface that implemented the I/O subsystem.
microprocessor and MicroVAX 78132 floating-point coprocessor, but later Firefly systems used the faster CVAX 78034 microprocessors, CVAX Floating Point Chips (floating-point coprocessors). The processor boards communicated with each other and the memory via the MBus. The components used in the processor boards of the original Firefly were the same as those originally designed for the MicroVAX II system.
The caches in the Firefly were direct-mapped for simplicity and to support multiprocessing; they used the Firefly protocol
to ensure cache coherency
. The caches on the MicroVAX processor boards had a capacity of 16 KB (4,096 4-byte lines) and were implemented with eleven 2 KB (4-bit by 4,096-word) SRAMs and twenty transistor–transistor logic (TTL) devices. The cache control logic was implemented with fifteen devices, mostly consisting of programmable array logic
(PAL) devices. The caches on CVAX processor boards differed only in the capacity: 64 KB (16,384 4-byte lines) and were implemented with 8 KB (4-bit by 16,384-word) SRAMs.
and over the MBus. Memory was implemented by one to four memory modules that connect to the MBus. The original Firefly had a master memory module with a capacity of 4 MB and up to three slave memory modules of the same capacity for a memory capacity of 4 to 16 MB. Later Firefly systems used a memory module with a capacity of 32 MB, for a memory capacity of 32 to 128 MB. The memory access time in the original MicroVAX-based Firefly was 400 ns, while the CVAX version had a memory access time of 200 ns.
(DMA) to access the memory though the cache of the main processor. The Firefly's I/O devices were: a monochrome display controller (MDC), a buffered controller for magnetic disk drives, the RQDX3 and an DEQNA Ethernet controller.
While DEC used existing components for most of the I/O system, the display controller was designed specifically for the Firefly by the project's engineers who felt that no existing product met their performance requirements. There were two displayer controllers, one providing color graphics, and the other monochrome graphics. These controllers operated by checking a work queue set up in the memory using DMA, providing fully symmetric access to the display hardware by all processors.
The monochrome display controller (MDC) was contained on a board half as large as the processor boards and was capable of achieving a resolution of 1024 by 768 pixels. It contained a 16-bit 29116 microprocessor clocked at 10 MHz with a 10 KB memory containing 2,048 40-bit words of microinstruction memory. A 1024 by 1024-pixel frame buffer was implemented with VRAM
s, with three quarters used to hold the display bitmap
with the rest available for the display manager or used to cache
fonts.
The 29116 microprocessor periodically checked a work queue set up in the memory using DMA and executed commands from that queue. The commands performed BitBlt operations within the frame buffer, between the system memory and frame buffer and were also used to paint characters from the font cache.
The display hardware also provided an interface for a keyboard and mouse. Sixty times per second, the MDC wrote to the memory the position of the mouse and an unencoded bitmap representing the state of the keyboard. As a result of implementing the MDC as an I/O device, the Firefly supported multiple display controllers in one system connected to multiple monitors.
that used a kernel
named the Nub, and the Trestle window manager
. One of the features of Taos was that it supported the Ultrix
system call interface, allowed existing Ultrix binaries compiled for the MicroVAX
to run unmodified on the Firefly. In contrast to Ultrix, Topaz supported processes with multiple threads which could span multiple processors, and the Taos system could run both Ultrix and Topaz applications at the same time. Modula-2+
, (an extension to the Modula-2
language) was used to program Topaz and Topaz based applications.
Shared memory
In computing, shared memory is memory that may be simultaneously accessed by multiple programs with an intent to provide communication among them or avoid redundant copies. Depending on context, programs may run on a single processor or on multiple separate processors...
asymmetric multiprocessor workstation
Workstation
A workstation is a high-end microcomputer designed for technical or scientific applications. Intended primarily to be used by one person at a time, they are commonly connected to a local area network and run multi-user operating systems...
, developed by the Systems Research Center
DEC Systems Research Center
The Systems Research Center was a research laboratory created by Digital Equipment Corporation in 1984, in Palo Alto, California....
, a research organization within Digital Equipment Corporation
Digital Equipment Corporation
Digital Equipment Corporation was a major American company in the computer industry and a leading vendor of computer systems, software and peripherals from the 1960s to the 1990s...
. The first version built contained up to seven MicroVAX 78032
MicroVAX 78032
The MicroVAX 78032 is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented a subset of the VAX instruction set architecture . The 78032 was used exclusively in DEC's VAX-based systems, starting with the MicroVAX II in 1985...
microprocessors. The cache from each of the microprocessors kept a consistent view of the same main memory using a cache coherency
Cache coherency
In computing, cache coherence refers to the consistency of data stored in local caches of a shared resource.When clients in a system maintain caches of a common memory resource, problems may arise with inconsistent data. This is particularly true of CPUs in a multiprocessing system...
algorithm, the Firefly protocol
Firefly protocol
The Firefly cache coherence protocol is the schema used in the DEC Firefly multiprocessor workstation, developed by DEC Systems Research Center. This protocol uses a write-through policy.- States :...
. The second version of the Firefly used faster CVAX 78034 microprocessors.
Hardware description
The Firefly was an asymmetric multiprocessor computer as only one of the microprocessors had access to a Q-BusQ-Bus
The Q-bus was one of several bus technologies used with PDP and MicroVAX computer systems manufactured by the Digital Equipment Corporation of Maynard, Massachusetts....
interface that implemented the I/O subsystem.
Processors
The Firefly contained a primary processor board and zero, one, two or three secondary processor boards. These processor boards were 8 by 10 inches large. The primary processor board contained a microprocessor, its floating-point coprocessor and cache, and the Q-Bus control logic. The secondary processor boards each contained two microprocessors, their floating-point coprocessors and caches. The original Firefly processor boards used the MicroVAX 78032MicroVAX 78032
The MicroVAX 78032 is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented a subset of the VAX instruction set architecture . The 78032 was used exclusively in DEC's VAX-based systems, starting with the MicroVAX II in 1985...
microprocessor and MicroVAX 78132 floating-point coprocessor, but later Firefly systems used the faster CVAX 78034 microprocessors, CVAX Floating Point Chips (floating-point coprocessors). The processor boards communicated with each other and the memory via the MBus. The components used in the processor boards of the original Firefly were the same as those originally designed for the MicroVAX II system.
The caches in the Firefly were direct-mapped for simplicity and to support multiprocessing; they used the Firefly protocol
Firefly protocol
The Firefly cache coherence protocol is the schema used in the DEC Firefly multiprocessor workstation, developed by DEC Systems Research Center. This protocol uses a write-through policy.- States :...
to ensure cache coherency
Cache coherency
In computing, cache coherence refers to the consistency of data stored in local caches of a shared resource.When clients in a system maintain caches of a common memory resource, problems may arise with inconsistent data. This is particularly true of CPUs in a multiprocessing system...
. The caches on the MicroVAX processor boards had a capacity of 16 KB (4,096 4-byte lines) and were implemented with eleven 2 KB (4-bit by 4,096-word) SRAMs and twenty transistor–transistor logic (TTL) devices. The cache control logic was implemented with fifteen devices, mostly consisting of programmable array logic
Programmable Array Logic
The term Programmable Array Logic is used to describe a family of programmable logic device semiconductors used to implement logic functions in digital circuits introduced by Monolithic Memories, Inc. in March 1978. MMI obtained a registered trademark on the term PAL for use in "Programmable...
(PAL) devices. The caches on CVAX processor boards differed only in the capacity: 64 KB (16,384 4-byte lines) and were implemented with 8 KB (4-bit by 16,384-word) SRAMs.
Memory
Processors in the Firefly communicated with the main memory through their individual cachesCPU cache
A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations...
and over the MBus. Memory was implemented by one to four memory modules that connect to the MBus. The original Firefly had a master memory module with a capacity of 4 MB and up to three slave memory modules of the same capacity for a memory capacity of 4 to 16 MB. Later Firefly systems used a memory module with a capacity of 32 MB, for a memory capacity of 32 to 128 MB. The memory access time in the original MicroVAX-based Firefly was 400 ns, while the CVAX version had a memory access time of 200 ns.
I/O
I/O devices were connected to the system via the Q-Bus, whose 22-bit address space was mapped onto the 24-bit memory address space of the Firefly by using mapping registers controlled by the master processor. The devices used direct memory accessDirect memory access
Direct memory access is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit ....
(DMA) to access the memory though the cache of the main processor. The Firefly's I/O devices were: a monochrome display controller (MDC), a buffered controller for magnetic disk drives, the RQDX3 and an DEQNA Ethernet controller.
While DEC used existing components for most of the I/O system, the display controller was designed specifically for the Firefly by the project's engineers who felt that no existing product met their performance requirements. There were two displayer controllers, one providing color graphics, and the other monochrome graphics. These controllers operated by checking a work queue set up in the memory using DMA, providing fully symmetric access to the display hardware by all processors.
The monochrome display controller (MDC) was contained on a board half as large as the processor boards and was capable of achieving a resolution of 1024 by 768 pixels. It contained a 16-bit 29116 microprocessor clocked at 10 MHz with a 10 KB memory containing 2,048 40-bit words of microinstruction memory. A 1024 by 1024-pixel frame buffer was implemented with VRAM
VRAM
Video RAM, or VRAM, is a dual-ported variant of dynamic RAM , which was once commonly used to store the framebuffer in some graphics adapters....
s, with three quarters used to hold the display bitmap
Bitmap
In computer graphics, a bitmap or pixmap is a type of memory organization or image file format used to store digital images. The term bitmap comes from the computer programming terminology, meaning just a map of bits, a spatially mapped array of bits. Now, along with pixmap, it commonly refers to...
with the rest available for the display manager or used to cache
Cache
In computer engineering, a cache is a component that transparently stores data so that future requests for that data can be served faster. The data that is stored within a cache might be values that have been computed earlier or duplicates of original values that are stored elsewhere...
fonts.
The 29116 microprocessor periodically checked a work queue set up in the memory using DMA and executed commands from that queue. The commands performed BitBlt operations within the frame buffer, between the system memory and frame buffer and were also used to paint characters from the font cache.
The display hardware also provided an interface for a keyboard and mouse. Sixty times per second, the MDC wrote to the memory the position of the mouse and an unencoded bitmap representing the state of the keyboard. As a result of implementing the MDC as an I/O device, the Firefly supported multiple display controllers in one system connected to multiple monitors.
Software
Both variants of the Firefly used system software called Topaz, which consisted of multiple components such as the Taos operating systemOperating system
An operating system is a set of programs that manage computer hardware resources and provide common services for application software. The operating system is the most important type of system software in a computer system...
that used a kernel
Kernel (computing)
In computing, the kernel is the main component of most computer operating systems; it is a bridge between applications and the actual data processing done at the hardware level. The kernel's responsibilities include managing the system's resources...
named the Nub, and the Trestle window manager
Window manager
A window manager is system software that controls the placement and appearance of windows within a windowing system in a graphical user interface. Most window managers are designed to help provide a desktop environment...
. One of the features of Taos was that it supported the Ultrix
Ultrix
Ultrix was the brand name of Digital Equipment Corporation's native Unix systems. While ultrix is the Latin word for avenger, the name was chosen solely for its sound.-History:...
system call interface, allowed existing Ultrix binaries compiled for the MicroVAX
MicroVAX
The MicroVAX was a family of low-end minicomputers developed and manufactured by Digital Equipment Corporation . The first model, the MicroVAX I, was introduced in 1984...
to run unmodified on the Firefly. In contrast to Ultrix, Topaz supported processes with multiple threads which could span multiple processors, and the Taos system could run both Ultrix and Topaz applications at the same time. Modula-2+
Modula-2+
Modula-2+ is a programming language descended from the Modula-2 language. It was developed at DEC Systems Research Center and Acorn Computers Ltd Research Centre in Palo Alto, California. Modula-2+ is Modula-2 with exceptions and threads. The group who developed the language was led by P...
, (an extension to the Modula-2
Modula-2
Modula-2 is a computer programming language designed and developed between 1977 and 1980 by Niklaus Wirth at ETH Zurich as a revision of Pascal to serve as the sole programming language for the operating system and application software for the personal workstation Lilith...
language) was used to program Topaz and Topaz based applications.