Delay Insensitive Minterm Synthesis
Encyclopedia
Invented by David E. Muller, the DIMS (Delay Insensitive Minterm Synthesis) system is an asynchronous design methodology making the least possible timing assumptions. Assuming only the Quasi-Delay-Insensitive delay model the generated designs need little if any timing hazard testing. The basis for DIMS is the use of two wires to represent each bit of data. This is known as a Dual-Rail data encoding. Parts of the system communicate using the early four-phase asynchronous protocol.
The construction of DIMS logic gates comprises generating every possible minterm using a row of C-element
s and then gathering the outputs of these using OR gate
s which generate the true and false output signals. With two dual-rail inputs the gate would be composed of four two-input C-elements. A three input gate uses eight three-input C-elements.
Latches are constructed using two C-elements to store the data and an OR gate to acknowledge the input once the data has been latched by attaching as its inputs the data output wires. The acknowledge from the forward stage is inverted and passed to the C-elements to allow them to reset once the computation has completed. This latch design is known as the 'half latch'. Other asynchronous latches provide a higher data capacity and levels of decoupling.
DIMS designs are large and slow but they have the advantage of being very robust.
The construction of DIMS logic gates comprises generating every possible minterm using a row of C-element
C-element
The Muller C-element, or Muller C-gate, is a commonly used asynchronous logic component originally designed by David E. Muller. It applies logical operations on the inputs and has hysteresis. The output of the C-element reflects the inputs when the states of all inputs match. The output then...
s and then gathering the outputs of these using OR gate
OR gate
The OR gate is a digital logic gate that implements logical disjunction - it behaves according to the truth table to the right. A HIGH output results if one or both the inputs to the gate are HIGH . If neither input is HIGH, a LOW output results...
s which generate the true and false output signals. With two dual-rail inputs the gate would be composed of four two-input C-elements. A three input gate uses eight three-input C-elements.
Latches are constructed using two C-elements to store the data and an OR gate to acknowledge the input once the data has been latched by attaching as its inputs the data output wires. The acknowledge from the forward stage is inverted and passed to the C-elements to allow them to reset once the computation has completed. This latch design is known as the 'half latch'. Other asynchronous latches provide a higher data capacity and levels of decoupling.
DIMS designs are large and slow but they have the advantage of being very robust.
Further reading
- Jens Sparsø, Steve Furber: "Principles of Asynchronous Circuit Design"; Kluwer, Dordrecht (2001); chapter 5.5.1. ISBN 0792376137