Delay insensitive circuit
Encyclopedia
A delay insensitive circuit is a type of asynchronous circuit which performs a logic
operation often within a computing processor chip. Instead of using clock signal
s or other global control signals, the sequencing of computation in delay insensitive circuit is determined by the data flow.
Typically handshake
signals are used to indicate the readiness of such a circuit to accept new data (the previous computation is complete) and the delivery of such data by the requesting function. Similarly there may be output handshake signals indicating the readiness of the result and the safe delivery of the result to the next stage in a computational chain or pipeline.
In a delay insensitive circuit, there is therefore no need to provide a clock signal to determine a starting time for a computation. Instead, the arrival of data to the input of a sub-circuit triggers the computation to start. Consequently, the next computation can be initiated immediately when the result of the first computation is completed.
The main advantage of such circuits is their ability to optimise processing of activities that can take arbitrary
periods of time depending on the data or requested function. An example of a process with a variable time for completion would be mathematical division
or recovery of data where such data might be in a cache
.
The Delay-Insensitive (DI) class is the most robust of all asynchronous circuit
delay models. It makes no assumptions on the delay of wires or gates. In this model all transitions on gates or wires must be acknowledged before transitioning again. This condition stops unseen transitions from occurring. In DI circuits any transition on an input to a gate must be seen on the output of the gate before a subsequent transition on that input is allowed to happen. This forces some input states or sequences to become illegal. For example OR gates must never go into the state where both inputs are one, as the entry and exit from this state will not be seen on the output of the gate. Although this model is very robust, no practical circuits are possible due to the heavy restrictions. Instead the Quasi-Delay-Insensitive model is the smallest compromise model yet capable of generating useful computing circuits. For this reason circuits are often incorrectly referred to as Delay-Insensitive when they are Quasi-Delay-Insensitive.
Delay-insensitive circuits usually use dual-rail encodings for data.
There are a variety of other delay-insensitive codes, such as constant-weight code
s and the Berger code
.
Logic
In philosophy, Logic is the formal systematic study of the principles of valid inference and correct reasoning. Logic is used in most intellectual activities, but is studied primarily in the disciplines of philosophy, mathematics, semantics, and computer science...
operation often within a computing processor chip. Instead of using clock signal
Clock signal
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...
s or other global control signals, the sequencing of computation in delay insensitive circuit is determined by the data flow.
Typically handshake
Handshake
A handshake is a short ritual in which two people grasp one of each other's like hands, in most cases accompanied by a brief up and down movement of the grasped hands.-History:...
signals are used to indicate the readiness of such a circuit to accept new data (the previous computation is complete) and the delivery of such data by the requesting function. Similarly there may be output handshake signals indicating the readiness of the result and the safe delivery of the result to the next stage in a computational chain or pipeline.
In a delay insensitive circuit, there is therefore no need to provide a clock signal to determine a starting time for a computation. Instead, the arrival of data to the input of a sub-circuit triggers the computation to start. Consequently, the next computation can be initiated immediately when the result of the first computation is completed.
The main advantage of such circuits is their ability to optimise processing of activities that can take arbitrary
Arbitrary
Arbitrariness is a term given to choices and actions subject to individual will, judgment or preference, based solely upon an individual's opinion or discretion.Arbitrary decisions are not necessarily the same as random decisions...
periods of time depending on the data or requested function. An example of a process with a variable time for completion would be mathematical division
Division (mathematics)
right|thumb|200px|20 \div 4=5In mathematics, especially in elementary arithmetic, division is an arithmetic operation.Specifically, if c times b equals a, written:c \times b = a\,...
or recovery of data where such data might be in a cache
Cache
In computer engineering, a cache is a component that transparently stores data so that future requests for that data can be served faster. The data that is stored within a cache might be values that have been computed earlier or duplicates of original values that are stored elsewhere...
.
The Delay-Insensitive (DI) class is the most robust of all asynchronous circuit
Asynchronous circuit
An asynchronous circuit is a circuit in which the parts are largely autonomous. They are not governed by a clock circuit or global clock signal, but instead need only wait for the signals that indicate completion of instructions and operations. These signals are specified by simple data transfer...
delay models. It makes no assumptions on the delay of wires or gates. In this model all transitions on gates or wires must be acknowledged before transitioning again. This condition stops unseen transitions from occurring. In DI circuits any transition on an input to a gate must be seen on the output of the gate before a subsequent transition on that input is allowed to happen. This forces some input states or sequences to become illegal. For example OR gates must never go into the state where both inputs are one, as the entry and exit from this state will not be seen on the output of the gate. Although this model is very robust, no practical circuits are possible due to the heavy restrictions. Instead the Quasi-Delay-Insensitive model is the smallest compromise model yet capable of generating useful computing circuits. For this reason circuits are often incorrectly referred to as Delay-Insensitive when they are Quasi-Delay-Insensitive.
Delay-insensitive circuits usually use dual-rail encodings for data.
There are a variety of other delay-insensitive codes, such as constant-weight code
Constant-weight code
In coding theory, a constant-weight code, also called an m of n code, is an error detection and correction code where all codewords share the same Hamming weight. The theory is closely connected to that of designs...
s and the Berger code
Berger code
In telecommunication, a Berger code is a unidirectional error detecting code, named after its inventor, J. M. Berger. Berger codes can detect all unidirectional errors. Unidirectional errors are errors that only flip ones into zeroes or only zeroes into ones, such as in asymmetric channels...
.
External links
- self-clocking signalSelf-clocking signalIn telecommunications and electronics, a self-clocking signal is one that can be decoded without the need for a separate clock signal or other source of synchronization...
- "Delay-Insensitive Codes -- An Overview" by Tom Verhoeff
- "TITAC: Design of A Quasi-Delay-Insensitive Microprocessor" by Takashi Nanya et al. 1994
- "A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems" by Pedro A. Molina and Peter Y. K. Cheung 1997
- "Quasi-Delay-Insensitive Circuits are Turing-Complete" by Manohar, Rajit and Martin, Alain J. (1995)
- "EDIS, the Encyclopedia of Delay-Insensitive Systems" edited by Tom Verhoeff