Domino logic
Encyclopedia
Domino logic is a CMOS
-based evolution of the dynamic logic
techniques which were based on either PMOS or NMOS transistor
s. It allows a rail-to-rail logic swing. It was developed to speed up circuits.
In Dynamic Logic, a problem arises when cascading one gate to the next. The precharge "1" state of the first gate may cause the second gate to discharge prematurely, before the first gate has reached its correct state. This uses up the "precharge" of the second gate, which cannot be restored until the next clock cycle, so there is no recovery from this error.
There are various solutions to the problem of how to cascade dynamic logic gates. One solution is Domino Logic, which inserts an ordinary static inverter between stages. While this might seem to defeat the point of dynamic logic, since the inverter has a PFET (one of the main goals of Dynamic Logic is to avoid PFETs where possible, due to speed), there are two reasons it works well. First, there is no fanout to multiple PFETs. The dynamic gate connects to exactly one inverter, so the gate is still very fast. And since the inverter connects to only NFETs in dynamic logic gates, it too is very fast. Second, the PFET in an inverter can be made smaller than in some types of logic gates.
In a domino logic cascade structure consisting of several stages, the evaluation of each stage ripples the next stage evaluation, similar to a domino falling one after the other. Once fallen, the node states cannot return to "1" (until the next clock cycle) just as dominos, once fallen, cannot stand up. The structure is hence called Domino CMOS Logic. It contrasts with other solutions to the cascade problem in which cascading is interrupted by clocks or other means.
Important Domino Logic features include:
CMOS
Complementary metal–oxide–semiconductor is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits...
-based evolution of the dynamic logic
Dynamic logic (digital logic)
In integrated circuit design, dynamic logic is a design methodology in combinatorial logic circuits, particularly those implemented in MOS technology. It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances...
techniques which were based on either PMOS or NMOS transistor
Transistor
A transistor is a semiconductor device used to amplify and switch electronic signals and power. It is composed of a semiconductor material with at least three terminals for connection to an external circuit. A voltage or current applied to one pair of the transistor's terminals changes the current...
s. It allows a rail-to-rail logic swing. It was developed to speed up circuits.
In Dynamic Logic, a problem arises when cascading one gate to the next. The precharge "1" state of the first gate may cause the second gate to discharge prematurely, before the first gate has reached its correct state. This uses up the "precharge" of the second gate, which cannot be restored until the next clock cycle, so there is no recovery from this error.
There are various solutions to the problem of how to cascade dynamic logic gates. One solution is Domino Logic, which inserts an ordinary static inverter between stages. While this might seem to defeat the point of dynamic logic, since the inverter has a PFET (one of the main goals of Dynamic Logic is to avoid PFETs where possible, due to speed), there are two reasons it works well. First, there is no fanout to multiple PFETs. The dynamic gate connects to exactly one inverter, so the gate is still very fast. And since the inverter connects to only NFETs in dynamic logic gates, it too is very fast. Second, the PFET in an inverter can be made smaller than in some types of logic gates.
In a domino logic cascade structure consisting of several stages, the evaluation of each stage ripples the next stage evaluation, similar to a domino falling one after the other. Once fallen, the node states cannot return to "1" (until the next clock cycle) just as dominos, once fallen, cannot stand up. The structure is hence called Domino CMOS Logic. It contrasts with other solutions to the cascade problem in which cascading is interrupted by clocks or other means.
Important Domino Logic features include:
- They have smaller areas than conventional CMOS logic (as does all Dynamic Logic).
- Parasitic capacitances are smaller so that higher operating speeds are possible.
- Operation is free of glitches as each gate can make only one transition.
- Only non-inverting structures are possible because of the presence of inverting buffer.
- Charge distribution may be a problem.