EISC
Encyclopedia
The EISC is a compressed code processor
architecture for embedded
applications. It has both the properties of RISC architecture,simplicity, and that of CISC
processor,expenability. The architecture is developed by Advanced Digital Chips Inc., Seoul, Korea.
by ARM and MIPS16 by MIPS
and so on. In short, compressed code architectures have shorter length instructions for controlling the data path. Many compressed code architectures suffer from insufficient immediate operand fields.
While achieving high code density and a low memory access rate, the EISC architecture adopts a novel and terse scheme to resolve the problem of insufficient immediate operand fields of the compressed code architectures. The EISC uses an efficient fixed length 16-bit instruction set for 32-bit data processing. To resolve the problem of insufficient immediate operand fields in a concise way, EISC uses an independent instruction called load extension register (LERI), which consists of a 2-bit opcode and a 14-bit immediate value.
The LERI instruction extends the immediate field by loading an immediate value to a special register called the extension register. By using LERI instructions, the EISC architecture can make the program code more compact than the competing architectures, since the frequency of LERI instructions is less than 20% in many programs. In addition, EISC does not require instructions for switching its processor mode between the compressed instruction mode and the normal instruction mode. (For competing architectures, extra mode-changing instructions are added to use specific instructions such as MAC instructions.)
There exist SE(simple EISC) series and AE(Advanced EISC) series.
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
architecture for embedded
Embedded system
An embedded system is a computer system designed for specific control functions within a larger system. often with real-time computing constraints. It is embedded as part of a complete device often including hardware and mechanical parts. By contrast, a general-purpose computer, such as a personal...
applications. It has both the properties of RISC architecture,simplicity, and that of CISC
Complex instruction set computer
A complex instruction set computer , is a computer where single instructions can execute several low-level operations and/or are capable of multi-step operations or addressing modes within single instructions...
processor,expenability. The architecture is developed by Advanced Digital Chips Inc., Seoul, Korea.
Extendable Instruction Set
In embedded applications, code density is a golden goal since higher code density means less memory traffic and die area for embedded memory can be reduced. To improve code density, compressed code architectures have appeared such as THUMBThumb
The thumb is the first digit of the hand. When a person is standing in the medical anatomical position , the thumb is the lateral-most digit...
by ARM and MIPS16 by MIPS
MIPS Technologies
MIPS Technologies, Inc. , formerly MIPS Computer Systems, Inc., is most widely known for developing the MIPS architecture and a series of pioneering RISC chips. MIPS provides processor architectures and cores for digital home, networking and mobile applications.MIPS Computer Systems Inc. was...
and so on. In short, compressed code architectures have shorter length instructions for controlling the data path. Many compressed code architectures suffer from insufficient immediate operand fields.
While achieving high code density and a low memory access rate, the EISC architecture adopts a novel and terse scheme to resolve the problem of insufficient immediate operand fields of the compressed code architectures. The EISC uses an efficient fixed length 16-bit instruction set for 32-bit data processing. To resolve the problem of insufficient immediate operand fields in a concise way, EISC uses an independent instruction called load extension register (LERI), which consists of a 2-bit opcode and a 14-bit immediate value.
The LERI instruction extends the immediate field by loading an immediate value to a special register called the extension register. By using LERI instructions, the EISC architecture can make the program code more compact than the competing architectures, since the frequency of LERI instructions is less than 20% in many programs. In addition, EISC does not require instructions for switching its processor mode between the compressed instruction mode and the normal instruction mode. (For competing architectures, extra mode-changing instructions are added to use specific instructions such as MAC instructions.)
Instruction Set Architecture Family
The EISC has 16-bit, 32-bit and 64-bit instruction set architecture family.There exist SE(simple EISC) series and AE(Advanced EISC) series.
- SE1608: 16-bit simple EISC family. 3-operand instruction set architecture. Not a compressed code architecture but it also uses LERI instruction to fully support 16-bit immediate value diretly.
- SE3208: 32-bit simple EISC family. 3-operand instruction set architecture. 8 GPRs.
- AE32000: 32-bit Advanced EISC family for embedded microprocessing market. 2-operand instruction set architecture. 16 GPRs. It also has SIMD-DSP capability. The Newest instruction set architecture is AE32000C (AE32000-revision C)
- AE64000: 64-bit Advanced EISC family for embedded microprocessing market especially robot and multimedia market.
Class Core Process Clock Freq. Average IPC Peak MIPS Gate Counts Power Consumption(@0.18 μm) Pipelines SIMD-DSP SE SE1608 16-bit CPU 70 MHz@0.18 μm 8K 3 stages SE3208 32-bit CPU 70 MHz@0.18 μm 13K 3 stages AE AE32000C-Tiny up to 100 MHz@0.18 μm over 0.8 110 MIPS@100 MHz 26~30K under 0.15 mW/MHz 3 stages AE32000C-Lucida up to 150 MHz@0.18 μm over 0.87 145 MIPS@130 MHz 50~88K under 0.30 mW/MHz 5 stages SIMD-DSP AE32000C-Empress up to 300 MHz@0.13 μm over 0.78 120K under 0.38 mW/MHz 9 stages SIMD-DSP
Related links
- ADChips Inc., The inventor of EISC processor
- EISC technology overview in ADCUS inc.
- EISC Studio2: Free Integrated Development Environment(IDE) software for EISC processor (Supported OS: Windows)
- ECOMI: Precompiled CrossCompiler Toolchain for 32bit EISC processor AE32000 series (Needs Cygwin under Windows)
Related papers
- High-performance extendable instruction set computing
- AE32000B: a Fully Synthesizable 32-Bit Embedded Microprocessor Core in ETRI Journal, Volume 25, Number 5, October 2003
- A DSP-enhanced 32-bit embedded microprocessor
- "An automated, reconfigurable, low-power RFID tag" compares the EISC architecture with other architectures
- Design of a DSP Unit for 32-bit Embedded EISC Microprocessor
- Supports for Processing Media Data in Embedded Processors