Intel 8253
Encyclopedia
The Intel 8253 and 8254 are Programmable Interval Timer
s (PITs), which perform timing and counting functions. They were primarily designed for the Intel 8080
/8085
-processors, but later used in x86-systems. They (or an equivalent circuit embedded in a larger chip) are found in all IBM PC compatible
s.
chipset. In some modern chipsets, this change may show up as measurable timing differences in accessing a PIT using the x86 I/O address space. Reads and writes to such a PIT's registers in the I/O address space may complete much faster.
Newer motherboards also include a counter through the Advanced Configuration and Power Interface
(ACPI), a counter on the Local Advanced Programmable Interrupt Controller (Local APIC), and a High Precision Event Timer
. The CPU itself also provides the Time Stamp Counter
(TSC) facility.
s), which are labeled as Counter 0, Counter 1 and Counter 2 . Each counter has 2 input pins – CLK (clock
input) and GATE – and 1-pin, OUT, for data output. The 3 counters are 16-bit down counters independent of each other, and can be easily read by the CPU.
The first counter (selected by setting A1=A0=0, see Control Word Register below) helps generate a clock
interrupt. The second counter (A1=0, A0=1) assists in generating timing, which will be used to refresh the DRAM
memory. The last counter (A1=1, A0=0) generates tones for the PC speaker
.
Besides the counters, a typical Intel 8253 microchip also contains the following components:
.
Operation mode of the PIT is changed by setting the above hardware signals. For example, to write to the Control Word Register, one needs to set /CS=0, /RD=1, /WR=0, A1=A0=1.
Port 53h R/W – second chip ...
This register contains the programmed information which will be sent (by the microprocessor
) to the device. It defines how the PIT logically works. Each access to these ports takes about 1 µs.
To initialize the counters, the microprocessor must write a control word (CW) in this register. This can be done by setting proper values for the pins of the Read/Write Logic block and then by sending the control word to the Data/Bus Buffer block.
The control word register contains 8 bits, labeled D7..D0 (D7 is the MSB
).
When setting the PIT, the microprocessor first sends a control message, then a count message to the PIT. The counting process will start after the PIT has received these messages, and, in some cases, if it detects the rising edge from the GATE input signal.
On PCs the address for timer0 (chip) is at port 40h..43h like described and the second timer1 (chip) is at 50h..53h.
The Status Byte is read like a 8 bit counter value (port 40h..42h R).
The OUT pin is set low after the Control Word is written, and counting starts one clock cycle after the COUNT programmed. OUT remains low until the counter reaches 0, at which point OUT will be set high until the counter is reloaded or the Control Word is written. The Gate signal should remain active high for normal counting. If Gate goes low counting get terminated and current count is latched till Gate pulse goes high again.
OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin the one-shot pulse, and will remain low until the Counter reaches zero. OUT will then go high and remain high until the CLK pulse after the next trigger.
After writing the Control Word and initial count, the Counter is armed. A trigger results in loading the Counter and setting OUT low on the next CLK pulse, thus starting the one-shot pulse. An initial count of N will result in a one-shot pulse N CLK cycles in duration.
The one-shot is retriggerable, hence OUT will remain low for N CLK pulses after any trigger. The one-shot pulse can be repeated without rewriting the same count into the counter. GATE has no effect on OUT. If a new count is written to the Counter during a oneshot pulse, the current one-shot is not affected unless the counter is retriggered. In that case, the Counter is loaded with the new count and the oneshot pulse continues until the new count expires.
Like other modes, counting process will start the next clock cycle after COUNT is sent. OUT will then remain high until the counter reaches 1, and will go low for one clock pulse. OUT will then go high again, and the whole process repeats itself.
The time between the high pulses depends on the preset count in the counter's register, and is calculated using the following formula:
Value to be loaded into counter =
Note that the values in the COUNT register range from
to 1; the register never reaches zero.
Suppose n is the number loaded into the counter (the COUNT message), the output will be
After receiving the Control Word and COUNT, the output will be set high. Once the device detects a rising edge on the GATE input, it will start counting. When the counter reaches 0, the output will go low for one clock cycle – after that it will become high again, to repeat the cycle on the next rising edge of GATE.
The timer that is used by the system on x86 PCs is Channel 0, and its clock ticks at a theoretical value of 1193181.8181... Hz
, i.e. one third of the NTSC
color subcarrier
frequency, which comes from dividing the system clock (14.31818 MHz) by 12. This is a holdover of the very first CGA
PCs – they derived all necessary frequencies from a single quartz
crystal, and to make TV output possible, this quartz had to run at a multiple of the NTSC color subcarrier frequency.
As stated above, Channel 0 is implemented as a counter. Typically, the initial value of the counter is set by sending bytes to the Control, then Data I/O Port registers (the value 36h sent to port 43h, then the low byte to port 40h, and port 40h again for the high byte). The counter counts down to zero, then sends a hardware interrupt (IRQ 0, INT 8) to the CPU. The counter then resets to its initial value and begins to count down again. The fastest possible interrupt frequency is a little over a megahertz. The slowest possible frequency, which is also the one normally used by computers running MS-DOS
or compatible operating systems, is about 18.2 Hz. Under these real mode
operating systems, the BIOS accumulates the number of INT 8 calls that it receives in real mode address 0040:006c, which can be read by a program.
As a timer counts down, its value can also be read directly by reading its I/O port twice, first for the low byte, and then for the high byte. However, in free-running counter applications such as in the x86 PC, it is necessary to first write a latch command for the desired channel to the control register, so that both bytes read will belong to one and the same value.
Programmable Interval Timer
In computing and in embedded systems, a programmable interval timer is a counter which triggers an interrupt when it reaches the programmed count.- Common features :...
s (PITs), which perform timing and counting functions. They were primarily designed for the Intel 8080
Intel 8080
The Intel 8080 was the second 8-bit microprocessor designed and manufactured by Intel and was released in April 1974. It was an extended and enhanced variant of the earlier 8008 design, although without binary compatibility...
/8085
Intel 8085
The Intel 8085 is an 8-bit microprocessor introduced by Intel in 1977. It was binary-compatible with the more-famous Intel 8080 but required less supporting hardware, thus allowing simpler and less expensive microcomputer systems to be built....
-processors, but later used in x86-systems. They (or an equivalent circuit embedded in a larger chip) are found in all IBM PC compatible
IBM PC compatible
IBM PC compatible computers are those generally similar to the original IBM PC, XT, and AT. Such computers used to be referred to as PC clones, or IBM clones since they almost exactly duplicated all the significant features of the PC architecture, facilitated by various manufacturers' ability to...
s.
History
The 8253 was used in IBM PC compatibles since their introduction in 1981. In modern times, this PIT is not included as a separate chip in an x86 PC. Rather, its functionality is included as part of the motherboard's southbridgeSouthbridge (computing)
The southbridge is one of the two chips in the core logic chipset on a personal computer motherboard, the other being the northbridge. The southbridge typically implements the slower capabilities of the motherboard in a northbridge/southbridge chipset computer architecture. In Intel chipset...
chipset. In some modern chipsets, this change may show up as measurable timing differences in accessing a PIT using the x86 I/O address space. Reads and writes to such a PIT's registers in the I/O address space may complete much faster.
Newer motherboards also include a counter through the Advanced Configuration and Power Interface
Advanced Configuration and Power Interface
In computing, the Advanced Configuration and Power Interface specification provides an open standard for device configuration and power management by the operating system....
(ACPI), a counter on the Local Advanced Programmable Interrupt Controller (Local APIC), and a High Precision Event Timer
High Precision Event Timer
The High Precision Event Timer is a hardware timer used in personal computers. It was developed jointly by Intel and Microsoft and has been incorporated in PC chipsets since circa 2005...
. The CPU itself also provides the Time Stamp Counter
Time Stamp Counter
The Time Stamp Counter is a 64-bit register present on all x86 processors since the Pentium. It counts the number of ticks since reset. The instruction "RDTSC" returns the TSC in EDX:EAX. In x86_64 mode, RDTSC also clears the higher 32 bits of RAX. Its opcode is 0F 31. Pentium competitors such as...
(TSC) facility.
Features
The timer has three counters, called channels. Each channel can be programmed to operate in one of six modes. Once programmed, the channels can perform their tasks independently. The timer is usually assigned to IRQ-0 (highest priority hardware interrupt) because of the critical function it performs and because so many devices depend on it.Counters
There are 3 counters (or timerTimer
A timer is a specialized type of clock. A timer can be used to control the sequence of an event or process. Whereas a stopwatch counts upwards from zero for measuring elapsed time, a timer counts down from a specified time interval, like an hourglass.Timers can be mechanical, electromechanical,...
s), which are labeled as Counter 0, Counter 1 and Counter 2 . Each counter has 2 input pins – CLK (clock
Clock
A clock is an instrument used to indicate, keep, and co-ordinate time. The word clock is derived ultimately from the Celtic words clagan and clocca meaning "bell". A silent instrument missing such a mechanism has traditionally been known as a timepiece...
input) and GATE – and 1-pin, OUT, for data output. The 3 counters are 16-bit down counters independent of each other, and can be easily read by the CPU.
The first counter (selected by setting A1=A0=0, see Control Word Register below) helps generate a clock
Clock signal
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...
interrupt. The second counter (A1=0, A0=1) assists in generating timing, which will be used to refresh the DRAM
Dram
Dram or DRAM may refer to:As a unit of measure:* Dram , an imperial unit of mass and volume* Armenian dram, a monetary unit* Dirham, a unit of currency in several Arab nationsOther uses:...
memory. The last counter (A1=1, A0=0) generates tones for the PC speaker
PC speaker
A PC speaker is a loudspeaker, built into some IBM PC compatible computers. The first IBM Personal Computer, model 5150, employed a standard 2.25 inch magnetic driven speaker. More recent computers use a piezoelectric speaker instead. The speaker allows software and firmware to provide...
.
Besides the counters, a typical Intel 8253 microchip also contains the following components:
Data/Bus Buffer
This block contains the logic to buffer the data bus to / from the microprocessor, and to the internal registers. It has 8 input pins, usually labelled as D7..D0, where D7 is the MSBMost significant bit
In computing, the most significant bit is the bit position in a binary number having the greatest value...
.
Read/Write Logic
The Read/Write Logic block has 5 pins, which are listed below. Notice that /X denotes an active low signal.- /RD: read signal
- /WR: write signal
- /CS: chip select signal
- A0, A1: address lines
Operation mode of the PIT is changed by setting the above hardware signals. For example, to write to the Control Word Register, one needs to set /CS=0, /RD=1, /WR=0, A1=A0=1.
Control Word Register
Port 43h R/WPort 53h R/W – second chip ...
This register contains the programmed information which will be sent (by the microprocessor
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
) to the device. It defines how the PIT logically works. Each access to these ports takes about 1 µs.
To initialize the counters, the microprocessor must write a control word (CW) in this register. This can be done by setting proper values for the pins of the Read/Write Logic block and then by sending the control word to the Data/Bus Buffer block.
The control word register contains 8 bits, labeled D7..D0 (D7 is the MSB
Most significant bit
In computing, the most significant bit is the bit position in a binary number having the greatest value...
).
| Bit# | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | Short Description |
|---|---|---|---|---|---|---|---|---|---|
| Name | SC1 | SC0 | RW1 | RW0 | M2 | M1 | M0 | BCD | |
| 0 | 0 | x | x | x | x | x | x | Counter 0 at port 40h R/W | |
| 0 | 1 | x | x | x | x | x | x | Counter 1 at port 41h R/W | |
| 1 | 0 | x | x | x | x | x | x | Counter 2 at port 42h R/W | |
| x | x | 0 | 0 | x | x | x | x | Counter Latch, value can be read out in the way RW1, RW0 was set before. The value is held until it is read out or overwritten. | |
| x | x | 0 | 1 | x | x | x | x | Read/Write bits 0..7 of counter value | |
| x | x | 1 | 0 | x | x | x | x | Read/Write bits 8..15 of counter value | |
| x | x | 1 | 1 | x | x | x | x | 2xRead/2xWrite bits 0..7 then 8..15 of counter value | |
| x | x | x | x | 0 | 0 | 0 | x | Mode 0: Interrupt on Terminal Count | |
| x | x | x | x | 0 | 0 | 1 | x | Mode 1: Hardware Retriggerable One-Shot | |
| x | x | x | x | 0 | 1 | 0 | x | Mode 2: Rate Generator | |
| x | x | x | x | 0 | 1 | 1 | x | Mode 3: Square Wave | |
| x | x | x | x | 1 | 0 | 0 | x | Mode 4: Software Triggered Strobe | |
| x | x | x | x | 1 | 0 | 1 | x | Mode 5: Hardware Triggered Strobe (Retriggerable) | |
| x | x | x | x | x | x | x | 0 | Counter is a 16 bit binary counter(0..65535,FFFFh) | |
| x | x | x | x | x | x | x | 1 | Counter is a 16 bit decimal counter 4 x 4bit decades(0..9999) | |
| Name | 1 | 1 | _____ count |
_____ status |
C2 | C1 | C0 | 0 | |
| 1 | 1 | 0 | 1 | x | x | x | 0 | Counter(C0..C2) value(s) can be read out. | |
| 1 | 1 | 1 | 0 | x | x | x | 0 | Counter's(C0..C2) state(s) can be read out. see below Status Byte |
|
| 1 | 1 | 0 | 0 | x | x | x | 0 | error |
When setting the PIT, the microprocessor first sends a control message, then a count message to the PIT. The counting process will start after the PIT has received these messages, and, in some cases, if it detects the rising edge from the GATE input signal.
On PCs the address for timer0 (chip) is at port 40h..43h like described and the second timer1 (chip) is at 50h..53h.
Status Byte
8 bitThe Status Byte is read like a 8 bit counter value (port 40h..42h R).
Bit# D7 D6 D5 D4 D3 D2 D1 D0
Name output null RW1 RW0 M2 M1 M0 BCD
count
-------------------------------------------
0 x x x x x x x Out Pin is 0
1 x x x x x x x Out Pin is 1
-------------------------------------------
x 0 x x x x x x The value of the latch is loaded into the counter.
A new value can be written to the latch.
x 1 x x x x x x Counter value is 0.
-------------------------------------------
x x = = = = = = like defined in the Control Word Register
Operation Modes
The D3, D2, and D1 bits of the Control Word set the operating mode of the timer. There are 6 modes in total; for modes 2 and 3, the D3 bit is ignored, so the missing modes 6 and 7 are aliases for modes 2 and 3. Notice that, for modes 0, 2, 3 and 4, GATE must be set to HIGH to enable counting. For mode 5, the rising edge of GATE starts the count. For details on each mode, see the reference links.Mode 0 (000): Interrupt on Terminal Count
Mode 0 is used for the generation of accurate time delay under software control.In this mode, the counter will start counting from the initial COUNT value loaded into it, down to 0. Counting rate is equal to the input clock frequency.The OUT pin is set low after the Control Word is written, and counting starts one clock cycle after the COUNT programmed. OUT remains low until the counter reaches 0, at which point OUT will be set high until the counter is reloaded or the Control Word is written. The Gate signal should remain active high for normal counting. If Gate goes low counting get terminated and current count is latched till Gate pulse goes high again.
Mode 1 (001): Programmable One Shot
In this mode 8253 can be used as monostable multivibrator. GATE input is used as trigger input.OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin the one-shot pulse, and will remain low until the Counter reaches zero. OUT will then go high and remain high until the CLK pulse after the next trigger.
After writing the Control Word and initial count, the Counter is armed. A trigger results in loading the Counter and setting OUT low on the next CLK pulse, thus starting the one-shot pulse. An initial count of N will result in a one-shot pulse N CLK cycles in duration.
The one-shot is retriggerable, hence OUT will remain low for N CLK pulses after any trigger. The one-shot pulse can be repeated without rewriting the same count into the counter. GATE has no effect on OUT. If a new count is written to the Counter during a oneshot pulse, the current one-shot is not affected unless the counter is retriggered. In that case, the Counter is loaded with the new count and the oneshot pulse continues until the new count expires.
Mode 2 (X10): Rate Generator
In this mode, the device acts as a divide-by-n counter, which is commonly used to generate a real-time clock interrupt.Like other modes, counting process will start the next clock cycle after COUNT is sent. OUT will then remain high until the counter reaches 1, and will go low for one clock pulse. OUT will then go high again, and the whole process repeats itself.
The time between the high pulses depends on the preset count in the counter's register, and is calculated using the following formula:
Value to be loaded into counter =
Note that the values in the COUNT register range from
to 1; the register never reaches zero.Mode 3 (X11): Square Wave Generator
This mode is similar to mode 2. However, the duration of the high and low clock pulses of the output will be different from mode 2.Suppose n is the number loaded into the counter (the COUNT message), the output will be
- high for
counts, and low for 
counts, if n is even. - high for
counts, and low for 
counts, if n is odd.
Mode 4 (100): Software Triggered Strobe
After Control Word and COUNT is loaded, the output will remain high until the counter reaches zero. The counter will then generate a low pulse for 1 clock cycle (a strobe) – after that the output will become high again.Mode 5 (101): Hardware Triggered Strobe
This mode is similar to mode 4. However, the counting process is triggered by the GATE input.After receiving the Control Word and COUNT, the output will be set high. Once the device detects a rising edge on the GATE input, it will start counting. When the counter reaches 0, the output will go low for one clock cycle – after that it will become high again, to repeat the cycle on the next rising edge of GATE.
Programming Considerations
On x86 PCs, many video card BIOS and system BIOS will reprogram the second counter for their own use. Reprogramming typically happens during video mode changes, when the video BIOS may be executed, and during system management mode and power saving state changes, when the system BIOS may be executed. This prevents any serious alternative uses of the timer's second counter on many x86 systems.The timer that is used by the system on x86 PCs is Channel 0, and its clock ticks at a theoretical value of 1193181.8181... Hz
Hertz
The hertz is the SI unit of frequency defined as the number of cycles per second of a periodic phenomenon. One of its most common uses is the description of the sine wave, particularly those used in radio and audio applications....
, i.e. one third of the NTSC
NTSC
NTSC, named for the National Television System Committee, is the analog television system that is used in most of North America, most of South America , Burma, South Korea, Taiwan, Japan, the Philippines, and some Pacific island nations and territories .Most countries using the NTSC standard, as...
color subcarrier
Subcarrier
A subcarrier is a separate analog or digital signal carried on a main radio transmission, which carries extra information such as voice or data. More technically, it is an already-modulated signal, which is then modulated into another signal of higher frequency and bandwidth...
frequency, which comes from dividing the system clock (14.31818 MHz) by 12. This is a holdover of the very first CGA
Color Graphics Adapter
The Color Graphics Adapter , originally also called the Color/Graphics Adapter or IBM Color/Graphics Monitor Adapter, introduced in 1981, was IBM's first color graphics card, and the first color computer display standard for the IBM PC....
PCs – they derived all necessary frequencies from a single quartz
Quartz
Quartz is the second-most-abundant mineral in the Earth's continental crust, after feldspar. It is made up of a continuous framework of SiO4 silicon–oxygen tetrahedra, with each oxygen being shared between two tetrahedra, giving an overall formula SiO2. There are many different varieties of quartz,...
crystal, and to make TV output possible, this quartz had to run at a multiple of the NTSC color subcarrier frequency.
As stated above, Channel 0 is implemented as a counter. Typically, the initial value of the counter is set by sending bytes to the Control, then Data I/O Port registers (the value 36h sent to port 43h, then the low byte to port 40h, and port 40h again for the high byte). The counter counts down to zero, then sends a hardware interrupt (IRQ 0, INT 8) to the CPU. The counter then resets to its initial value and begins to count down again. The fastest possible interrupt frequency is a little over a megahertz. The slowest possible frequency, which is also the one normally used by computers running MS-DOS
MS-DOS
MS-DOS is an operating system for x86-based personal computers. It was the most commonly used member of the DOS family of operating systems, and was the main operating system for IBM PC compatible personal computers during the 1980s to the mid 1990s, until it was gradually superseded by operating...
or compatible operating systems, is about 18.2 Hz. Under these real mode
Real mode
Real mode, also called real address mode, is an operating mode of 80286 and later x86-compatible CPUs. Real mode is characterized by a 20 bit segmented memory address space and unlimited direct software access to all memory, I/O addresses and peripheral hardware...
operating systems, the BIOS accumulates the number of INT 8 calls that it receives in real mode address 0040:006c, which can be read by a program.
As a timer counts down, its value can also be read directly by reading its I/O port twice, first for the low byte, and then for the high byte. However, in free-running counter applications such as in the x86 PC, it is necessary to first write a latch command for the desired channel to the control register, so that both bytes read will belong to one and the same value.
Literature
- Gilluwe, Frank van. The Undocumented PC. A-W Developers Press, 1997. ISBN 0-201-47950-8