In electronics, an adder

Adder (electronics)

In electronics, an adder or summer is a digital circuit that performs addition of numbers.In many computers and other kinds of processors, adders are used not only in the arithmetic logic unit, but also in other parts of the processor, where they are used to calculate addresses, table indices, and...

 is a combinatorial or sequential logic element which computes the n-bit sum of two numbers. The family of Ling adders is a particularly fast adder and is designed using H. Ling's equations and generally implemented in BiCMOS

BiCMOS

BiCMOS is an evolved semiconductor technology that integrates two formerly separate semiconductor technologies - those of the analog bipolar junction transistor and the digital CMOS transistor - in a single integrated circuit device....

. Samuel Naffziger of Hewlett Packard presented an innovative 64 bit adder in 0.5 µm CMOS

CMOS

Complementary metal–oxide–semiconductor is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits...

 based on Ling's equations at ISSCC 1996. The Naffziger adder's delay was less than 1 nanosecond

Nanosecond

A nanosecond is one billionth of a second . One nanosecond is to one second as one second is to 31.7 years.The word nanosecond is formed by the prefix nano and the unit second. Its symbol is ns....

, or 7 FO4

FO4

Fan-out of 4 is a process independent delay metric used in digital CMOS technologies.Fan out = Cload / CinCload = total MOS gate capacitance driven by the logic gate under considerationCin = the MOS gate capacitance of the logic gate under consideration...

. See Naffzinger's paper below for more details.

External links

1. H. Ling, "High Speed Binary Parallel Adder", IEEE Transactions on Electronic Computers, EC-15, p.799-809, October, 1966.
2. H. Ling, "High-Speed Binary Adder", IBM J. Res. Dev., vol.25, p.156-66, 1981.
3. R. W. Doran, "Variants on an Improved Carry Look-Ahead Adder", IEEE Transactions on Computers, Vol.37, No.9, September 1988.
4. N. T. Quach, M. J. Flynn, "High-Speed Addition in CMOS", IEEE Transactions on Computers, Vol.41, No.12, December, 1992.
5. S. Naffziger, "A Sub-Nanosecond 0.5um 64b Adder Design", Digest of Technical Papers, 1996 IEEE International Solid-State Circuits Conference, San Francisco, 8-10 Feb. 1996, p.362 –363.
6. S. Naffziger, "High Speed Addition Using Ling's Equations and Dynamic CMOS Logic", U.S. Patent No. 5,719,803, Issued: February 17, 1998.