Mano machine
Encyclopedia
The Mano machine is a theoretical computer
described by M. Morris Mano. It contains a central processing unit
, random access memory, and an input-output bus. Its limited instruction set and small address space limit it to purely academic consideration.
, such as the same address space, only one accumulator register, and many similar instructions. The Mano machine has a 4096x16 shared data/program memory segment requiring a 12-bit address bus. The data bus is 16 bits. There are 8-bit input/output buses for external communication, and associated interrupt flags.
There is one 16-bit accumulator register, and single-bit registers (latches) for addition carry and system halt.
Each instruction is 16 bits long [4 nybbles, or 1 word]. This means that memory referencing instructions contain 4 bits of op-code data, and 12 bits dedicated to the address.
that determines the processor's micro-operations. The canonical implementation of the state machine is an excellent candidate for reduction, and can also be re-implemented as a pipelined
processor.
Computer
A computer is a programmable machine designed to sequentially and automatically carry out a sequence of arithmetic or logical operations. The particular sequence of operations can be changed readily, allowing the computer to solve more than one kind of problem...
described by M. Morris Mano. It contains a central processing unit
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
, random access memory, and an input-output bus. Its limited instruction set and small address space limit it to purely academic consideration.
Characteristics
The Mano machine is similar in many respects to the PDP-8PDP-8
The 12-bit PDP-8 was the first successful commercial minicomputer, produced by Digital Equipment Corporation in the 1960s. DEC introduced it on 22 March 1965, and sold more than 50,000 systems, the most of any computer up to that date. It was the first widely sold computer in the DEC PDP series of...
, such as the same address space, only one accumulator register, and many similar instructions. The Mano machine has a 4096x16 shared data/program memory segment requiring a 12-bit address bus. The data bus is 16 bits. There are 8-bit input/output buses for external communication, and associated interrupt flags.
There is one 16-bit accumulator register, and single-bit registers (latches) for addition carry and system halt.
Instruction set
There are 25 instructions that fall into 3 categories: direct / indirect memory referencing operations, register referencing operations, and input/output / interrupt operations.Each instruction is 16 bits long [4 nybbles, or 1 word]. This means that memory referencing instructions contain 4 bits of op-code data, and 12 bits dedicated to the address.
| Bit 15 | Bits 14-12 | Bits 11-0 | Mnemonic | Description |
|---|---|---|---|---|
| 0 | 0 | (Direct address) | AND | And direct memory to accumulator |
| 0 | 1 | (Direct address) | ADD | Add direct memory to accumulator (affects carry bit) |
| 0 | 2 | (Direct address) | LDA | Load direct memory to accumulator |
| 0 | 3 | (Direct address) | STA | Store accumulator to direct memory |
| 0 | 4 | (Direct address) | BUN | Unconditionally branch to direct memory |
| 0 | 5 | (Direct address) | BSA | Store current program counter to direct memory and branch to following address |
| 0 | 6 | (Direct address) | ISZ | Increment value in direct memory and skip next instruction if the sum is zero |
| 1 | 0-6 | (Indirect address) | Indirect addressing versions of the above instructions | |
| 0 | 7 | 800 | CLA | Clear the accumulator |
| 0 | 7 | 400 | CLE | Clear the carry bit |
| 0 | 7 | 200 | CMA | Complement the accumulator |
| 0 | 7 | 100 | CME | Complement the carry bit |
| 0 | 7 | 080 | CIR | Circulate accumulator right (through carry bit) |
| 0 | 7 | 040 | CIL | Circulate accumulator left (through carry bit) |
| 0 | 7 | 020 | INC | Increment accumulator (does not affect carry bit) |
| 0 | 7 | 010 | SPA | Skip next instruction if accumulator is positive |
| 0 | 7 | 008 | SNA | Skip next instruction if accumulator is negative |
| 0 | 7 | 004 | SZA | Skip next instruction if accumulator is zero |
| 0 | 7 | 002 | SZE | Skip next instruction if carry bit is zero |
| 0 | 7 | 001 | HLT | Halt computer by clearing the halt bit latch |
| 1 | 7 | 800 | INP | Input from character bus to accumulator |
| 1 | 7 | 400 | OUT | Output from accumulator to character bus |
| 1 | 7 | 200 | SKI | Skip next instruction if input flag is set |
| 1 | 7 | 100 | SKO | Skip next instruction if output flag is set |
| 1 | 7 | 080 | ION | Enable interrupts |
| 1 | 7 | 040 | IOF | Disable interrupts |
Applications to computer optimization theory
The machine specifications include a finite state machineFinite state machine
A finite-state machine or finite-state automaton , or simply a state machine, is a mathematical model used to design computer programs and digital logic circuits. It is conceived as an abstract machine that can be in one of a finite number of states...
that determines the processor's micro-operations. The canonical implementation of the state machine is an excellent candidate for reduction, and can also be re-implemented as a pipelined
Instruction pipeline
An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput ....
processor.