Memory level parallelism
Encyclopedia
Memory Level Parallelism or MLP is a term in computer architecture referring to the ability to have pending multiple memory operations, in particular cache
misses or translation lookaside buffer
misses, at the same time.
In a single processor, MLP may be considered a form of ILP, instruction level parallelism
. However, ILP is often mixed up with superscalar
, the ability to execute more than one instruction at the same time. E.g. a processor such as the Intel Pentium Pro
is five-way superscalar, with the ability to start executing five different microinstructions in a given cycle, but it can handle four different cache misses for up to 20 different load microinstructions at any time.
It is possible to have a machine that is not superscalar but which nevertheless has high MLP.
Arguably a machine that has no ILP, which is not superscalar, which executes one instruction at a time in a non-pipelined manner, but which performs hardware prefetching (not software instruction level prefetching) exhibits MLP (due to multiple prefetches outstanding) but not ILP. This is because there are multiple memory _operations_ outstanding, but not _instructions_. Instructions are often mixed up with operations.
Furthermore, multiprocessor and multithreaded computer systems may be said to exhibit MLP and ILP due to parallelism - but not intra-thread, single process, ILP and MLP. Often, however, we restrict the terms MLP and ILP to refer to extracting such parallelism from what appears to be non-parallel single threaded code.
Cache
In computer engineering, a cache is a component that transparently stores data so that future requests for that data can be served faster. The data that is stored within a cache might be values that have been computed earlier or duplicates of original values that are stored elsewhere...
misses or translation lookaside buffer
Translation Lookaside Buffer
A translation lookaside buffer is a CPU cache that memory management hardware uses to improve virtual address translation speed. All current desktop and server processors use a TLB to map virtual and physical address spaces, and it is ubiquitous in any hardware which utilizes virtual memory.The...
misses, at the same time.
In a single processor, MLP may be considered a form of ILP, instruction level parallelism
Instruction level parallelism
Instruction-level parallelism is a measure of how many of the operations in a computer program can be performed simultaneously. Consider the following program: 1. e = a + b 2. f = c + d 3. g = e * f...
. However, ILP is often mixed up with superscalar
Superscalar
A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate...
, the ability to execute more than one instruction at the same time. E.g. a processor such as the Intel Pentium Pro
Pentium Pro
The Pentium Pro is a sixth-generation x86 microprocessor developed and manufactured by Intel introduced in November 1, 1995 . It introduced the P6 microarchitecture and was originally intended to replace the original Pentium in a full range of applications...
is five-way superscalar, with the ability to start executing five different microinstructions in a given cycle, but it can handle four different cache misses for up to 20 different load microinstructions at any time.
It is possible to have a machine that is not superscalar but which nevertheless has high MLP.
Arguably a machine that has no ILP, which is not superscalar, which executes one instruction at a time in a non-pipelined manner, but which performs hardware prefetching (not software instruction level prefetching) exhibits MLP (due to multiple prefetches outstanding) but not ILP. This is because there are multiple memory _operations_ outstanding, but not _instructions_. Instructions are often mixed up with operations.
Furthermore, multiprocessor and multithreaded computer systems may be said to exhibit MLP and ILP due to parallelism - but not intra-thread, single process, ILP and MLP. Often, however, we restrict the terms MLP and ILP to refer to extracting such parallelism from what appears to be non-parallel single threaded code.