There are several ways to organise memories with respect to the way they are connected to the cache

Cache

In computer engineering, a cache is a component that transparently stores data so that future requests for that data can be served faster. The data that is stored within a cache might be values that have been computed earlier or duplicates of original values that are stored elsewhere...

:

1. one-word-wide memory organisation
2. wide memory organisation
3. interleaved memory
   Interleaved memory
   Interleaved memory is a technique for compensating the relatively slow speed of DRAM. The CPU can access alternative sections immediately without waiting for memory to be cached. Multiple memory banks take turns supplying data....
   
    organisation
4. independent memory organisation

One-Word-Wide

The memory is one word wide and connected via a one word wide bus

Computer bus

In computer architecture, a bus is a subsystem that transfers data between components inside a computer, or between computers.Early computer buses were literally parallel electrical wires with multiple connections, but the term is now used for any physical arrangement that provides the same...

 to the cache(fastest memory).

Wide

The memory is more than one word wide (usually four words wide) and connected by an equally wide bus to the low level cache (which is also wide). From the cache multiple busses of one word wide go to a MUX

Mux

mux was a windowing system developed by Rob Pike at Bell Labs for the Ninth Edition Research Unix. mux is a predecessor of the Plan 9 windowing systems 8½ and rio, which retain its minimalist user interface.-External links :*...

which selects the correct bus to connect to the high level cache.

Interleaved

There are several memory banks which are one word wide, and one word wide bus. There is some logic in the memory that selects the correct bank to use when the memory gets accessed by the cache.

Memory interleaving is a way to distribute individual addresses over memory modules. Its aim is to keep the most of modules busy as computations proceed. With memory interleaving, the low-order k bits of the memory address select a module, and the high-order m bits name a location within that module. Hence, consecutive addresses are located in successive modules. A request to access consecutive memory locations can keep several modules busy at the same time.

Independent

There are several banks, which can all be accessed simultaneously by several buses.