NVAX
Encyclopedia
The NVAX is a microprocessor developed and fabricated by Digital Equipment Corporation
(DEC) that implemented the VAX
instruction set architecture (ISA). The NVAX was a high-end single-chip VAX microprocessor. A variant of the NVAX, the NVAX+, differed in the bus interface and external cache supported, but was otherwise identical in regards to microarchitecture. The NVAX is clocked at frequencies of 83.3 MHz (12 ns), 74.4 MHz (14 ns) and 62.5 MHz (16 ns), while the NVAX+ is clocked at a frequency of 90.9 MHz (11 ns).
The NVAX and NVAX+ was used in late-model VAX systems released in 1991 such as the MicroVAX 3100
, VAXstation 4000
, VAX 4000
, VAX 6000
, VAX 7000/10000
and VAXft
. Although Digital updated the design throughout the early 1990s, the processors and the VAX platform itself was ultimately superseded by the introduction of the DECchip 21064
, an implementation of the Alpha (then Alpha AXP) architecture, and the resulting systems in November 1992.
NVAX contained 1.3 million transistors on a die
measuring 16.2 by 14.6 mm in size (236.52 mm²). The die was fabricated in Digital's fourth-generation CMOS process, CMOS-4, a 0.75 µm process with three layers of aluminium interconnect. The NVAX is packaged in a 339-pin pin grid array
while the NVAX+ is packaged in a 431-pin pin grid array
that is compatible with the Alpha AXP-based DECchip 21064 microprocessor.
In 1994, a variant of the NVAX+, the NVAX++ (also known as NV5) was introduced in VAX 7000 Model 7x0 and VAX 10000 Model 7x0 systems. It operated at 133 MHz (7.5 ns) and was fabricated in Digital's fifth-generation CMOS process, CMOS-5, a 0.50 µm process. In 1996, a 170.9 MHz NV5 was introduced, used in the VAX 7000/10000 Model 8x0.
The I-box fetches and decodes VAX instructions. It also contains the 2 KB direct-mapped virtual instruction cache (VIC) and the 512-entry by 4-bit branch history table. The I-box aimed to fetch eight bytes of instruction data from the VIC during every cycle.
The E-box executes most non-floating-point instructions. It is controlled by microcode
from a 1,600-word control store
with the capability to patch 20 words.
The F-box executes floating-point instructions as well as 32-bit integer multiply instructions. It has a four-stage floating-point and integer multiply pipeline and a non-pipelined floating-point divider.
Digital Equipment Corporation
Digital Equipment Corporation was a major American company in the computer industry and a leading vendor of computer systems, software and peripherals from the 1960s to the 1990s...
(DEC) that implemented the VAX
VAX
VAX was an instruction set architecture developed by Digital Equipment Corporation in the mid-1970s. A 32-bit complex instruction set computer ISA, it was designed to extend or replace DEC's various Programmed Data Processor ISAs...
instruction set architecture (ISA). The NVAX was a high-end single-chip VAX microprocessor. A variant of the NVAX, the NVAX+, differed in the bus interface and external cache supported, but was otherwise identical in regards to microarchitecture. The NVAX is clocked at frequencies of 83.3 MHz (12 ns), 74.4 MHz (14 ns) and 62.5 MHz (16 ns), while the NVAX+ is clocked at a frequency of 90.9 MHz (11 ns).
The NVAX and NVAX+ was used in late-model VAX systems released in 1991 such as the MicroVAX 3100
MicroVAX
The MicroVAX was a family of low-end minicomputers developed and manufactured by Digital Equipment Corporation . The first model, the MicroVAX I, was introduced in 1984...
, VAXstation 4000
VAXstation
The VAXstation was a family of workstation computers developed and manufactured by Digital Equipment Corporation using processors implementing the VAX instruction set architecture .- VAXstation I :...
, VAX 4000
VAX 4000
The VAX 4000 was a family of low-end minicomputers developed and manufactured by Digital Equipment Corporation using microprocessors implementing the VAX instruction set architecture . The VAX 4000 succeeded the MicroVAX family...
, VAX 6000
VAX 6000
The VAX 6000 was a family of minicomputers developed and manufactured by Digital Equipment Corporation using processors implementing the VAX instruction set architecture...
, VAX 7000/10000
VAX 7000/10000
The VAX 7000 and VAX 10000 were a series of high-end multiprocessor minicomputers developed and manufactured by Digital Equipment Corporation , introduced in July 1992. These systems used microprocessors implementing the VAX instruction set architecture...
and VAXft
VAXft
The VAXft was a family of fault-tolerant minicomputers developed and manufactured by Digital Equipment Corporation using processors implementing the VAX instruction set architecture . "VAXft" stood for "Virtual Address Extension, fault tolerant". These systems ran the OpenVMS operating system, and...
. Although Digital updated the design throughout the early 1990s, the processors and the VAX platform itself was ultimately superseded by the introduction of the DECchip 21064
Alpha 21064
The Alpha 21064 is a microprocessor developed and fabricated by Digital Equipment Corporation that implemented the Alpha instruction set architecture . It was introduced as the DECchip 21064 before it was renamed in 1994. The 21064 is also known by its code name, EV4...
, an implementation of the Alpha (then Alpha AXP) architecture, and the resulting systems in November 1992.
NVAX contained 1.3 million transistors on a die
Die (integrated circuit)
A die in the context of integrated circuits is a small block of semiconducting material, on which a given functional circuit is fabricated.Typically, integrated circuits are produced in large batches on a single wafer of electronic-grade silicon or other semiconductor through processes such as...
measuring 16.2 by 14.6 mm in size (236.52 mm²). The die was fabricated in Digital's fourth-generation CMOS process, CMOS-4, a 0.75 µm process with three layers of aluminium interconnect. The NVAX is packaged in a 339-pin pin grid array
Pin grid array
A pin grid array, often abbreviated PGA, is a type of integrated circuit packaging. In a PGA, the package is square or roughly square, and the pins are arranged in a regular array on the underside of the package...
while the NVAX+ is packaged in a 431-pin pin grid array
Pin grid array
A pin grid array, often abbreviated PGA, is a type of integrated circuit packaging. In a PGA, the package is square or roughly square, and the pins are arranged in a regular array on the underside of the package...
that is compatible with the Alpha AXP-based DECchip 21064 microprocessor.
In 1994, a variant of the NVAX+, the NVAX++ (also known as NV5) was introduced in VAX 7000 Model 7x0 and VAX 10000 Model 7x0 systems. It operated at 133 MHz (7.5 ns) and was fabricated in Digital's fifth-generation CMOS process, CMOS-5, a 0.50 µm process. In 1996, a 170.9 MHz NV5 was introduced, used in the VAX 7000/10000 Model 8x0.
Microarchitecture
The NVAX is partitioned into the five semi-autonomous units, the I-box, E-box, F-box, M-box and C-box. The NVAX is macropipelined. Multiple VAX macroinstructions are processed in parallel by autonomous units, which have their own micropipelines.The I-box fetches and decodes VAX instructions. It also contains the 2 KB direct-mapped virtual instruction cache (VIC) and the 512-entry by 4-bit branch history table. The I-box aimed to fetch eight bytes of instruction data from the VIC during every cycle.
The E-box executes most non-floating-point instructions. It is controlled by microcode
Microcode
Microcode is a layer of hardware-level instructions and/or data structures involved in the implementation of higher level machine code instructions in many computers and other processors; it resides in special high-speed memory and translates machine instructions into sequences of detailed...
from a 1,600-word control store
Control store
A control store is the part of a CPU's control unit that stores the CPU's microprogram. It is usually accessed by a microsequencer. Early control stores were implemented as a diode-array accessed via address decoders, a form of read-only memory. This tradition dates back to the program timing...
with the capability to patch 20 words.
The F-box executes floating-point instructions as well as 32-bit integer multiply instructions. It has a four-stage floating-point and integer multiply pipeline and a non-pipelined floating-point divider.
Further reading
- Anderson, W. (1992). "Logical verification of the NVAX CPU chip design". Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors. pp. 306–309. ISBN 0-8186-3110-4.
- Badeau, R.W. et al. (1992). "A 100-MHz macropipelined VAX microprocessor". IEEE Journal of Solid-State Circuits, Volume 27, Issue 11. pp. 1585–1598. .
- Fox, Thomas F. (1994). "The design of high-performance microprocessors at Digital". Proceedings of the 31st Annual ACM-IEEE Design Automation Conference. pp. 586–591.