OpenVera
Encyclopedia
OpenVera is a dead Hardware Verification Language
developed, and managed by Synopsys
.
OpenVera(TM) is an interoperable, open hardware verification language for testbench creation. The OpenVera language was used as the basis for the advanced verification features in the IEEE Std. 1800 Systemverilog
Standard, for the benefit of the entire verification community including companies in the semiconductor, systems, IP and EDA industries along with verification services. OpenVera remains a widely adopted, evolving and well-supported hardware verification language.
OpenVera is an intuitive easy to learn language that combines the familiarity and strengths of HDLs, C++ and Java, with additional constructs targeted at functional verification making it ideal for developing testbenches, assertions and properties. OpenVera accelerates the creation of a verification environment by providing high-level constructs specifically designed for verification of complex SoCs. Designers create testbenches and assertions using OpenVera and EDA vendors create tools that are automatically interoperable.
OpenVera language reference manual (LRM) can be obtained at no cost, but modifications to the language must go through Synopsys
.
Hardware verification language
A Hardware Verification Language, or HVL, is a programming language used to verify the designs of electronic circuits written in a hardware description language. HVLs typically include features of a high-level programming language like C++ or Java as well as features for easy bit-level...
developed, and managed by Synopsys
Synopsys
Synopsys, Inc. is one of the largest companies in the Electronic Design Automation industry. Synopsys' first and best-known product is Design Compiler, a logic-synthesis tool. Synopsys offers a wide range of other products used in the design of an application-specific integrated circuit...
.
OpenVera(TM) is an interoperable, open hardware verification language for testbench creation. The OpenVera language was used as the basis for the advanced verification features in the IEEE Std. 1800 Systemverilog
SystemVerilog
In the semiconductor and electronic design industry, SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog.-History:...
Standard, for the benefit of the entire verification community including companies in the semiconductor, systems, IP and EDA industries along with verification services. OpenVera remains a widely adopted, evolving and well-supported hardware verification language.
OpenVera is an intuitive easy to learn language that combines the familiarity and strengths of HDLs, C++ and Java, with additional constructs targeted at functional verification making it ideal for developing testbenches, assertions and properties. OpenVera accelerates the creation of a verification environment by providing high-level constructs specifically designed for verification of complex SoCs. Designers create testbenches and assertions using OpenVera and EDA vendors create tools that are automatically interoperable.
OpenVera language reference manual (LRM) can be obtained at no cost, but modifications to the language must go through Synopsys
Synopsys
Synopsys, Inc. is one of the largest companies in the Electronic Design Automation industry. Synopsys' first and best-known product is Design Compiler, a logic-synthesis tool. Synopsys offers a wide range of other products used in the design of an application-specific integrated circuit...
.
Vendors supporting OpenVera
- Nusym TechnologyNusym TechnologyNusym Technology, Inc. is a company that produces intelligent verification software products, also known as intelligent testbench products, which are a form of functional verification that targets and maximizes test coverage of a logic design by automatically adapting the verification testbenches...
- SynopsysSynopsysSynopsys, Inc. is one of the largest companies in the Electronic Design Automation industry. Synopsys' first and best-known product is Design Compiler, a logic-synthesis tool. Synopsys offers a wide range of other products used in the design of an application-specific integrated circuit...
- Reference Verification Methodology (RVM)Reference Verification MethodologyThe Reference Verification Methodology is a complete set of metrics and methods for performing Functional verification of complex designs such as for Application-specific integrated circuits or other semiconductor devices...
External links
- http://www.open-vera.com/
- ASIC World Vera Tutorial
- Open Vera Tutorial