Runway bus
Encyclopedia
The Runway bus is a front side bus
developed by Hewlett-Packard
for use by its PA-RISC
microprocessor
family. The Runway bus is a 64-bit wide, split transaction, time multiplexed
address and data bus running at 120 MHz. This scheme was chosen by HP as they determined that a bus using separate address and data wires would have only delivered 20% more bandwidth for a 50% increase in pin count, which would have made microprocessors using the bus more expensive. The Runway bus was introduced with the release of the PA-7200
and was subsequently used by the PA-8000
, PA-8200, PA-8500, PA-8600 and PA-8700 microprocessors. Early implementations of the bus used in the PA-7200, PA-8000 and PA-8200 had a theoretical bandwidth of 960 MB/s. Beginning with the PA-8500, the Runway bus was revised to transmit on both rising and falling edges of a 125 MHz clock signal, which increased its theoretical bandwidth to 2 GB/s. The Runway bus was succeeded with the introduction of the PA-8800, which used the Itanium 2 bus.
Bus features
* 64-bit multiplexed address/data
* 20 bus protocol signals
* Supports cache coherency
* Three frequency options (1.0, 0.75 and 0.67 of CPU clock — 0.50 apparently was later added)
* Parity protection on address/data and control signal
* Each attached device contains its own arbitrator logic
* Split transactions, up to six transactions can be pending at once
* Snooping cache coherency protocol
* 1-4 processors "glueless" multi-processing (no support chips needed)
* 768 MB/s sustainable throughput, peak 960 MB/s at 120 MHz
* Runway+/Runway DDR: On PA-8500, PA-8600 and PA-8700, the bus operates in DDR (double data rate) mode,
* resulting in a peak bandwidth of about 2.0 GB/s (Runway+ or Runway DDR) with 125 MHz
Most machines use the Runway bus to connect the CPU
s directly to the IOMMU
(Astro, U2/Uturn or Java) and memory.
However, the N class and L3000 servers use an interface chip called Dew to bridge the Runway bus to the Merced bus that connects to the IOMMU and memory.
Front side bus
A front-side bus is a computer communication interface often used in computers during the 1990s and 2000s.It typically carries data between the central processing unit and a memory controller hub, known as the northbridge....
developed by Hewlett-Packard
Hewlett-Packard
Hewlett-Packard Company or HP is an American multinational information technology corporation headquartered in Palo Alto, California, USA that provides products, technologies, softwares, solutions and services to consumers, small- and medium-sized businesses and large enterprises, including...
for use by its PA-RISC
PA-RISC
PA-RISC is an instruction set architecture developed by Hewlett-Packard. As the name implies, it is a reduced instruction set computer architecture, where the PA stands for Precision Architecture...
microprocessor
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
family. The Runway bus is a 64-bit wide, split transaction, time multiplexed
Time-division multiplexing
Time-division multiplexing is a type of digital multiplexing in which two or more bit streams or signals are transferred apparently simultaneously as sub-channels in one communication channel, but are physically taking turns on the channel. The time domain is divided into several recurrent...
address and data bus running at 120 MHz. This scheme was chosen by HP as they determined that a bus using separate address and data wires would have only delivered 20% more bandwidth for a 50% increase in pin count, which would have made microprocessors using the bus more expensive. The Runway bus was introduced with the release of the PA-7200
PA-7200
The PA-7200 , code-named Thunderbird, is a microprocessor that implements the PA-RISC 1.1 instruction set architecture developed by Hewlett-Packard . It was introduced in early 1995, debuting in systems from HP...
and was subsequently used by the PA-8000
PA-8000
The PA-8000 , code-named Onyx, is a microprocessor developed and fabricated by Hewlett-Packard that implemented the PA-RISC 2.0 instruction set architecture . It was a completely new design with no circuitry derived from previous PA-RISC microprocessors...
, PA-8200, PA-8500, PA-8600 and PA-8700 microprocessors. Early implementations of the bus used in the PA-7200, PA-8000 and PA-8200 had a theoretical bandwidth of 960 MB/s. Beginning with the PA-8500, the Runway bus was revised to transmit on both rising and falling edges of a 125 MHz clock signal, which increased its theoretical bandwidth to 2 GB/s. The Runway bus was succeeded with the introduction of the PA-8800, which used the Itanium 2 bus.
Bus features
* 64-bit multiplexed address/data
* 20 bus protocol signals
* Supports cache coherency
* Three frequency options (1.0, 0.75 and 0.67 of CPU clock — 0.50 apparently was later added)
* Parity protection on address/data and control signal
* Each attached device contains its own arbitrator logic
* Split transactions, up to six transactions can be pending at once
* Snooping cache coherency protocol
* 1-4 processors "glueless" multi-processing (no support chips needed)
* 768 MB/s sustainable throughput, peak 960 MB/s at 120 MHz
* Runway+/Runway DDR: On PA-8500, PA-8600 and PA-8700, the bus operates in DDR (double data rate) mode,
* resulting in a peak bandwidth of about 2.0 GB/s (Runway+ or Runway DDR) with 125 MHz
Most machines use the Runway bus to connect the CPU
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
s directly to the IOMMU
IOMMU
In computing, an input/output memory management unit is a memory management unit that connects a DMA-capable I/O bus to the main memory...
(Astro, U2/Uturn or Java) and memory.
However, the N class and L3000 servers use an interface chip called Dew to bridge the Runway bus to the Merced bus that connects to the IOMMU and memory.