SPARC64 VI
Encyclopedia
The SPARC64 VI, code-named Olympus-C, is a microprocessor, developed by Fujitsu
. It implements the SPARC V9
instruction set architecture (ISA) and is compliant with the Joint Programming Specification (JSP1) developed by Fujitsu and Sun. It is used by Fujitsu and Sun Microsystems
in their SPARC Enterprise
M-class servers. The SPARC64 VI was succeeded by the SPARC64 VII (previously called the SPARC64 VI+) in July 2008.
The SPARC64 VI implements multithreading using two techniques, chip multiprocessing (CMP) and coarse-grained multi-threading which Fujitsu calls vertical multi-threading (VMT). The two cores both execute one thread each simultaneously, implementing CMP. Each core executes two threads, but only one of the two concurrent threads is executed at any given time. Which thread is executed is determined by time sharing or if the thread is executing a long latency operation, prompting the pipeline switches to another thread. Multithreading required duplication of the integer registers, floating-point registers, control registers and program counters so there is one set of each for every thread.
As the SPARC64 VI is a dual-core microprocessor, bandwidth had to be increased if the extra core is to contribute to performance significantly. The cores share a 6 MB on-die unified L2 cache. The L2 cache is 12-way set associative and has a 256-byte line size. The cache is accessed by two unidirectional buses. The read bus, which delivers data to the cores, is 256 bits wide; and the write bus is 128-bit wide. It also uses a new system bus, the Jupiter Bus.
The SPARC64 VI is the first SPARC microprocessor implementing a fused multiply–add (FMA), while the corresponding instructions performed separate multiplication and addition operations in previous versions.
(SOI) process.
(SMT), which replaces two-way coarse-grained multithreading, termed vertical multithreading (VMT) by Fujitsu. Thus, it can execute eight threads simultaneously.
Other changes include more RAS
features. The integer register file is now protected by ECC, and the number of error checkers has been increased to around 3,400.
It consists of 600 million transistors and is fabricated by Fujitsu in a 65 nm CMOS process.
The SPARC64 VII is socket compatible with its predecessor, the SPARC64 VI. Existing M-class servers are able to upgrade to the SPARC64 VII processors in the field.
Changes includes running at 3 GHz and containing 12 MB of Level 2 cache. The 50% increase in cache and 4% increase in clock speed results in approximately a 20% increase in overall performance.
The SPARC64 VII+ is socket compatible with its predecessor, the SPARC64 VII. Existing high-end M-class servers are able to upgrade to the SPARC64 VII+ processors in the field.
and is fabricated using Fujitsu's 45 nm process technology.
More on specifications and architecture is in this Fujitsu presentation.
is a supercomputer
being produced by Fujitsu
and located at the RIKEN Advanced Institute for Computational Science
campus in Kobe
, Japan
. It uses 8-core SPARC64 VIIIfx processor
s. In June 2011, TOP500
Project Committee announced that the K Computer topped the LINPACK
benchmark with the performance of 8.162 petaflops with a computing efficiency ratio of 93.0%, making it the fastest supercomputer in the world.
Fujitsu claims to be able to ship PRIMEHPC FX10 systems in January 2012.
Fujitsu
is a Japanese multinational information technology equipment and services company headquartered in Tokyo, Japan. It is the world's third-largest IT services provider measured by revenues....
. It implements the SPARC V9
SPARC
SPARC is a RISC instruction set architecture developed by Sun Microsystems and introduced in mid-1987....
instruction set architecture (ISA) and is compliant with the Joint Programming Specification (JSP1) developed by Fujitsu and Sun. It is used by Fujitsu and Sun Microsystems
Sun Microsystems
Sun Microsystems, Inc. was a company that sold :computers, computer components, :computer software, and :information technology services. Sun was founded on February 24, 1982...
in their SPARC Enterprise
SPARC Enterprise
The SPARC Enterprise series is a range of UNIX server computers co-developed by Sun Microsystems and Fujitsu introduced in 2007. They are marketed and sold by Sun Microsystems , Fujitsu, and Fujitsu Siemens Computers under the common brand of SPARC Enterprise, superseding Sun's Sun Fire and...
M-class servers. The SPARC64 VI was succeeded by the SPARC64 VII (previously called the SPARC64 VI+) in July 2008.
Description
The microprocessor has two cores. Each core is a modified SPARC64 V+ microprocessor. The process shrink enabled both cores and a secondary cache to be contained on a die.The SPARC64 VI implements multithreading using two techniques, chip multiprocessing (CMP) and coarse-grained multi-threading which Fujitsu calls vertical multi-threading (VMT). The two cores both execute one thread each simultaneously, implementing CMP. Each core executes two threads, but only one of the two concurrent threads is executed at any given time. Which thread is executed is determined by time sharing or if the thread is executing a long latency operation, prompting the pipeline switches to another thread. Multithreading required duplication of the integer registers, floating-point registers, control registers and program counters so there is one set of each for every thread.
As the SPARC64 VI is a dual-core microprocessor, bandwidth had to be increased if the extra core is to contribute to performance significantly. The cores share a 6 MB on-die unified L2 cache. The L2 cache is 12-way set associative and has a 256-byte line size. The cache is accessed by two unidirectional buses. The read bus, which delivers data to the cores, is 256 bits wide; and the write bus is 128-bit wide. It also uses a new system bus, the Jupiter Bus.
The SPARC64 VI is the first SPARC microprocessor implementing a fused multiply–add (FMA), while the corresponding instructions performed separate multiplication and addition operations in previous versions.
Physical
The SPARC64 VI consisted of 540 million transistors. The die measures 20.38 mm by 20.67 mm for an area of 421.25 mm2. It is fabricated by Fujitsu in a 90 nm, 10-layer copper, complementary metal–oxide–semiconductor (CMOS) silicon on insulatorSilicon on insulator
Silicon on insulator technology refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and thereby improving performance...
(SOI) process.
SPARC64 VII
The SPARC64 VII, code-named Jupiter, is a further development of the SPARC64 VI. It is a quad-core microprocessor. Each core is capable of two-way simultaneous multithreadingSimultaneous multithreading
Simultaneous multithreading, often abbreviated as SMT, is a technique for improving the overall efficiency of superscalar CPUs with hardware multithreading...
(SMT), which replaces two-way coarse-grained multithreading, termed vertical multithreading (VMT) by Fujitsu. Thus, it can execute eight threads simultaneously.
Other changes include more RAS
Reliability, Availability and Serviceability
reliability, availability, and serviceability are computer hardware engineering terms. It originated from IBM to advertise the robustness of their mainframe computers. The concept is often known by the acronym RAS....
features. The integer register file is now protected by ECC, and the number of error checkers has been increased to around 3,400.
It consists of 600 million transistors and is fabricated by Fujitsu in a 65 nm CMOS process.
The SPARC64 VII is socket compatible with its predecessor, the SPARC64 VI. Existing M-class servers are able to upgrade to the SPARC64 VII processors in the field.
SPARC64 VII+
The SPARC64 VII+, code-named Jupiter-E, is a further development of the SPARC64 VII. The VII+ holds the following features in common with the VII include: both are quad-core microprocessors where each core is capable of two-way simultaneous multithreading (SMT); a single socket can execute eight threads simultaneously; each core gets 128 KB Level 1 cache.Changes includes running at 3 GHz and containing 12 MB of Level 2 cache. The 50% increase in cache and 4% increase in clock speed results in approximately a 20% increase in overall performance.
The SPARC64 VII+ is socket compatible with its predecessor, the SPARC64 VII. Existing high-end M-class servers are able to upgrade to the SPARC64 VII+ processors in the field.
SPARC64 VIIIfx
The SPARC64 VIIIfx, code-named Venus, is an eight-core version of the SPARC64 VII. It includes a memory controller and 760 million transistors. The processor is capable of 128 GFLOPSFLOPS
In computing, FLOPS is a measure of a computer's performance, especially in fields of scientific calculations that make heavy use of floating-point calculations, similar to the older, simpler, instructions per second...
and is fabricated using Fujitsu's 45 nm process technology.
Specifications
- Registers: 192 integer, 256 floating point (8 single precision, 4 double precision), 3 interrupt.
- Address range: 41-bit (up to 1FFFFF00000h).
- Cache:
- L1: 32KiB 2-way data, 32KiB 2-way instruction (128 byte line), sectored
- L2: 5MiB 10-way (128 byte line), index hash sectored
- Translation lookaside bufferTranslation Lookaside BufferA translation lookaside buffer is a CPU cache that memory management hardware uses to improve virtual address translation speed. All current desktop and server processors use a TLB to map virtual and physical address spaces, and it is ubiquitous in any hardware which utilizes virtual memory.The...
: 16 fetch + 256 4-way store instruction, 512 4-way store data, no victim cache - Page sizes: 8KiB, 64KiB, 512KiB, 4MiB, 32MiB, 256MiB, 2GiB
- Translation storage buffer: Not supported in hardware
- SIMD: Max 2 parallel calculations, supports max 8 floating point values per cycle. Double precision floating point register can be used for single point calculations. Operands can be single or double precision floating point values.
More on specifications and architecture is in this Fujitsu presentation.
K supercomputer
The K computerK computer
The K computer – named for the Japanese word , which stands for 10 quadrillion – is a supercomputer being produced by Fujitsu at the RIKEN Advanced Institute for Computational Science campus in Kobe, Japan. In June 2011, TOP500 ranked K the world's fastest supercomputer, with a rating...
is a supercomputer
Supercomputer
A supercomputer is a computer at the frontline of current processing capacity, particularly speed of calculation.Supercomputers are used for highly calculation-intensive tasks such as problems including quantum physics, weather forecasting, climate research, molecular modeling A supercomputer is a...
being produced by Fujitsu
Fujitsu
is a Japanese multinational information technology equipment and services company headquartered in Tokyo, Japan. It is the world's third-largest IT services provider measured by revenues....
and located at the RIKEN Advanced Institute for Computational Science
RIKEN
is a large natural sciences research institute in Japan. Founded in 1917, it now has approximately 3000 scientists on seven campuses across Japan, the main one in Wako, just outside Tokyo...
campus in Kobe
Kobe
, pronounced , is the fifth-largest city in Japan and is the capital city of Hyōgo Prefecture on the southern side of the main island of Honshū, approximately west of Osaka...
, Japan
Japan
Japan is an island nation in East Asia. Located in the Pacific Ocean, it lies to the east of the Sea of Japan, China, North Korea, South Korea and Russia, stretching from the Sea of Okhotsk in the north to the East China Sea and Taiwan in the south...
. It uses 8-core SPARC64 VIIIfx processor
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
s. In June 2011, TOP500
TOP500
The TOP500 project ranks and details the 500 most powerful known computer systems in the world. The project was started in 1993 and publishes an updated list of the supercomputers twice a year...
Project Committee announced that the K Computer topped the LINPACK
LINPACK
LINPACK is a software library for performing numerical linear algebra on digital computers. It was written in Fortran by Jack Dongarra, Jim Bunch, Cleve Moler, and Gilbert Stewart, and was intended for use on supercomputers in the 1970s and early 1980s...
benchmark with the performance of 8.162 petaflops with a computing efficiency ratio of 93.0%, making it the fastest supercomputer in the world.
SPARC64 IXfx
Fujitsu introduced the SPARC64 IXfx processor in November 2011 when they revealed the PRIMEHPC FX10 supercomputer architecture. The IXfx processor have 16 cores, 12 MB shared L2 cache, run at 1.85 GHz, will reach a peak performance of 236,5 GFLOPS and will have a power efficiency of more than 2 GFLOPS per watt, e.g. 115 W per chip. It uses a SPARC v9 ISA, extended for high performance computing, with increased amounts of registers for integer and floating point computing.Fujitsu claims to be able to ship PRIMEHPC FX10 systems in January 2012.