A Serializer/Deserializer (SerDes pronounced sir-deez) is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction. The term "SerDes" generically refers to interfaces used in various technologies and applications.

Generic function

The basic SerDes function is made up of two functional blocks: the Parallel In Serial Out (PISO) block (aka Parallel-to-Serial converter) and the Serial In Parallel Out (SIPO) block (aka Serial-to-Parallel converter). There are 4 different SerDes architectures: (1) Parallel clock SerDes, (2) Embedded clock SerDes, (3) 8b/10b SerDes, (4) Bit interleaved SerDes.

The PISO (Parallel Input, Serial Output) block typically has a parallel clock input, a set of data input lines, and input data latches. It may use an internal or external Phase-locked loop (PLL)

Phase-locked loop

A phase-locked loop or phase lock loop is a control system that generates an output signal whose phase is related to the phase of an input "reference" signal. It is an electronic circuit consisting of a variable frequency oscillator and a phase detector...

 to multiply the incoming parallel clock up to the serial frequency. The simplest form of the PISO has a single shift register

Shift register

In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, which has the output of any one but the last flip-flop connected to the "data" input of the next one in the chain, resulting in a circuit that shifts by one position the one-dimensional "bit array" stored in...

 that receives the parallel data once per parallel clock, and shifts it out at the higher serial clock rate. Implementations may also have a double-buffered register.

The SIPO (Serial Input, Parallel Output) block typically has a receive clock output, a set of data output lines, and output data latches. The receive clock may have been recovered from the data by the serial clock recovery

Clock recovery

Some digital data streams, especially high-speed serial data streams are sent without an accompanying clock signal. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a phase-locked loop...

 technique. However, SerDes which do not transmit a clock use reference clock to lock the PLL to the correct Tx frequency, avoiding low harmonic frequencies present in the data stream

Data stream

In telecommunications and computing, a data stream is a sequence of digitally encoded coherent signals used to transmit or receive information that is in the process of being transmitted....

. The SIPO block then divides the incoming clock down to the parallel rate. Implementations typically have two registers connected as a double buffer. One register is used to clock in the serial stream, and the other is used to hold the data for the slower, parallel side.

Some types of SerDes include encoding/decoding blocks. The purpose of this encoding/decoding is typically to place at least statistical bounds on the rate of signal transitions to allow for easier clock recovery

Clock recovery

Some digital data streams, especially high-speed serial data streams are sent without an accompanying clock signal. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a phase-locked loop...

 in the receiver, to provide framing, and to provide DC balance.

Parallel clock SerDes

Parallel clock SerDes is normally used to serialize a parallel bus input along with data address & control signals. The serialized stream is sent along with a reference clock. The clock jitter tolerance at the serializer is 5-10 ps rms.

Embedded clock SerDes

An embedded clock SerDes serializes data and clock into a single stream. One cycle of clock signal is transmitted first, followed by the data bit stream; this creates a periodic rising edge at the start of the data bit stream. As the clock is explicitly embedded and can be recovered from the bit stream, the serializer (transmitter) clock jitter tolerance is relaxed to 80-120 ps rms, while the reference clock disparity at the deserializer can be +/-50000 ppm.

8b/10b SerDes

8b/10b SerDes maps each data byte to a 10bit code before serializing the data. The deserializer uses the reference clock to monitor the recovered clock from the bit stream. As the clock information is synthesized into the data bit stream, rather than explicitly embedding it, the serializer (transmitter) clock jitter tolerance is to 5-10 ps rms; and the reference clock disparity at the deserializer is +/-100ppm.

A common coding scheme used with SerDes is 8B/10B encoding

8B/10B encoding

In telecommunications, 8b/10b is a line code that maps 8-bit symbols to 10-bit symbols to achieve DC-balance and bounded disparity, and yet provide enough state changes to allow reasonable clock recovery. This means that the difference between the count of 1s and 0s in a string of at least 20 bits...

. This supports DC-balance, provides framing, and guarantees frequent transitions. The guaranteed transitions allow a receiver to extract the embedded clock. The control codes allow framing, typically on the start of a packet. The typical 8B/10B SerDes parallel side interfaces have one clock line, one control line and 8 data lines.

Such serializer-plus-8B/10B encoder, and deserializer-plus-decoder blocks are defined in the Gigabit Ethernet

Gigabit Ethernet

Gigabit Ethernet is a term describing various technologies for transmitting Ethernet frames at a rate of a gigabit per second , as defined by the IEEE 802.3-2008 standard. It came into use beginning in 1999, gradually supplanting Fast Ethernet in wired local networks where it performed...

 specification.

Another common coding scheme used with SerDes is 64B/66B encoding

64b/66b encoding

In data networking and transmission, 64b/66b is a line code that transforms 64-bit data to 66-bit line code to provide enough state changes to allow reasonable clock recovery and facilitate alignment of the data stream at the receiver....

. This scheme statistically delivers DC-balance and transitions through the use of a scrambler. Framing is delivered through the deterministic transitions of the added framing bits.

Such serializer-plus-64B/66B encoder and deserializer-plus-decoder blocks are defined in the 10 Gigabit Ethernet

10 Gigabit Ethernet

The 10 gigabit Ethernet computer networking standard was first published in 2002. It defines a version of Ethernet with a nominal data rate of 10 Gbit/s , ten times faster than gigabit Ethernet.10 gigabit Ethernet defines only full duplex point to point links which are generally connected by...

 specification. The transmit side comprises a 64B/66B encoder, a scrambler

Scrambler

In telecommunications, a scrambler is a device that transposes or inverts signals or otherwise encodes a message at the transmitter to make the message unintelligible at a receiver not equipped with an appropriately set descrambling device...

, and a gearbox that converts the 66B signal to a 16 bit interface. A further serializer then converts this 16 bit interface into a fully serial signal.

Bit interleaved SerDes

Bit interleaved SerDes multiplexes several slower serial data streams into faster serial streams, and the receiver demultiplexes the faster bit streams back to slower streams.

See also

• 8B/10B list of common protocols that use 8B/10B encoded SerDes
• SerDes Framer Interface
  SerDes Framer Interface
  SerDes Framer Interface is a standard for telecommunications abbreviated as SFI. Variants include:* SFI-4 or SerDes Framer Interface Level 4, a standardized Electrical Interface by the Optical Internetworking Forum for connecting a synchronous optical networking framer component to an optical...
  
  
• Multi-gigabit transceiver
  Multi-gigabit transceiver
  A Multi-Gigabit Transceiver is a SerDes capable of operating at serial bit rates above 1 Gigabit/second. MGTs are used increasingly for data communications because they can run over longer distances, use fewer wires, and thus have lower costs than parallel interfaces with equivalent data...