Source-Synchronous clocking refers to the technique of sourcing a clock along with the data. Specifically, the timing of unidirectional data signals is referenced to a clock (often called the strobe) sourced by the same device that generates those signals, and not to a global clock (i.e. generated by a bus master).

This type of clocking is common in high-speed interfaces between micro-chips, including DDR SDRAM

DDR SDRAM

Double data rate synchronous dynamic random access memory is a class of memory integrated circuits used in computers. DDR SDRAM has been superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which are either forward or backward compatible with DDR SDRAM, meaning that DDR2 or DDR3 memory modules...

, SGI XIO

XIO

XIO is a packet-based, high-performance computer bus employed by the SGI Origin 2000, Octane, Altix, Fuel and Tezro machines. The XIO forms a bus between high-performance system devices and the memory controller....

 interface, Intel Front Side Bus

Front side bus

A front-side bus is a computer communication interface often used in computers during the 1990s and 2000s.It typically carries data between the central processing unit and a memory controller hub, known as the northbridge....

 for the x86 and Itanium

Itanium

Itanium is a family of 64-bit Intel microprocessors that implement the Intel Itanium architecture . Intel markets the processors for enterprise servers and high-performance computing systems...

 processors, HyperTransport

HyperTransport

HyperTransport , formerly known as Lightning Data Transport , is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low-latency point-to-point link that was introduced on April 2, 2001...

, SPI-4.2

SPI-4.2

SPI-4.2 is a version of the System Packet Interface published by the Optical Internetworking Forum. It was designed to be used in systems that support OC-192 SONET interfaces and is sometimes used in 10 Gigabit Ethernet based systems....

 and many others.

Reasons for usage

A reason that source-synchronous clocking is useful is that it has been observed that all of the circuits within a given semiconductor device experience roughly the same process-voltage-temperature (PVT) variation. This means signal propagation delay experienced by the data through a device tracks the delay experienced by the clock through that same device over PVT. This advantage allows higher speed operation as compared to the traditional technique of providing the clock from a third device to both the transmitter and the receiver. Another benefit is that higher complexity data-recovery or clock-data-recovery circuits (such as PLLs) are not required when this technique is used.

Or rather than higher clock speeds, large systems that take advantage of source-synchronous clocking can have the benefit of a higher tolerance of PVT variation of its individual components.

Drawbacks

One drawback of using source-synchronous clocking is the creation of a separate clock-domain at the receiving device, namely the clock-domain of the strobe generated by the transmitting device. This strobe clock-domain is often not synchronous to the core clock domain of the receiving device. For proper operation of the received data with other data already present in the device, an additional stage of synchronization logic is required to transfer the received data into the core clock-domain of the receiving device. This stage can often be found alongside source synchronous logic. This usually results in greater system complexity compared to globally clocked systems, but the benefits are generally much greater than this increase in complexity.

Implementation Variations

In bi-directional data transfer buses, two opposing unidirectional strobes can be sent from each device. Often the strobe is free running in this case. That is, the strobe continues to toggle whether there is data being transferred or not.

Another variation is the sharing of the same bus to transfer the strobe. In this case the strobe can only be transferred by the device that is sending the data and may require transmission of pre-ambles and post-ambles to indicate the start and end of the strobes. (Example: DDR2

DDR2 SDRAM

DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM...

).

In large ASIC

ASIC

ASIC may refer to:* Application-specific integrated circuit, an integrated circuit developed for a particular use, as opposed to a customised general-purpose device.* ASIC programming language, a dialect of BASIC...

s or processors, multiple strobes and data groups (data bits that are associated to the same strobe) may exist between the same two devices to account for the slightly different PVT variations in different regions of the same die.

External links

• Overview of Memory Types and DDR Interface Design Implementation