Stream Processors, Inc
Encyclopedia
Stream Processors, Inc was a Silicon Valley
-based fabless semiconductor company
specializing in the design and manufacture of high-performance digital signal processor
s for applications including video
surveillance, multi-function printers and video conferencing.
The company ceased operations in 2009.
was initiated in
1995 by a research team led by MIT professor Bill Dally. In 1996, he moved to Stanford University
where he continued this work, receiving a multi-million dollar
grant from DARPA with additional resources from Intel and
Texas Instruments
to fund the development of a project called "Imagine"
- the first stream processor chip and accompanying compiler tools.
C programmable signal and image processor intended to provide both the performance density and efficiency of a
special-purpose processor (such as a hard-wired ASIC
). The project successfully demonstrated the advantages of stream processing. Details on the Imagine project and its results are posted
on the Stanford Imagine project page. The work also showed that a number of applications
ranging from wireless baseband processing, 3D graphics, encryption, IP
forwarding to video processing could take advantage of the efficiency of stream processing. This research inspired other
designs such as GPUs from ATI Technologies
as well as the Cell microprocessor
from Sony
, Toshiba
, and IBM
.
The main deliverables from the Imagine program included:
resulting technology. Stream Processors, Incorporated (SPI) was incorporated in
California in 2004. Professor Dally remained at Stanford and the company
hired industry veteran Chip Stearns http://www.streamprocessors.com/streamprocessors/Home/About/PressReleases/2004-12-13.html to become the President and CEO in December of that
year. Through June, 2006 SPI has been able to raise a total of $26M from a trio of notable venture capital
firms - Austin Ventures
, Norwest Venture Partners
and the Woodside Fund.
The company launched its first two products concurrently with the International Solid State
Circuits Conference (ISSCC) in February, 2006 and
has introduced two others since.
SPI has headquarters located in Sunnyvale, California
as well as a software development group (SPI Software Technologies Pvt. Ltd) located in Bangalore, India.
In January 2009 Co-Founder Prof. Bill Dally accepted a position as Chief Scientist with NVIDIA
Corporation. At the same time he
resigned as chairman. In an interview Dally reflected on his experiences with startups:
" I have done several chip startups myself. It’s getting hard. The ante is very high. If you do a chip startup, you need patient investors with very deep pockets. It’s many tens of millions of dollars to get to a first product and $50 million to get to profits. That’s very difficult to do because investors want an exit some multiple over that investment. I am hoping we return to the days of frequent IPOs and get beyond the fire-sale acquisitions. That’s not what you can see right now. If it’s a programmable chip, the cost is even more."
In the summer of 2009 CEO Stearns left the company and was replaced by Mike Fister, an executive with senior level experience at Cadence Design Systems
and Intel.
In September 2009 the company ceased operations.
are characterized by available data-parallelism, locality and a high computation
to global memory access ratio. Stream processing
exploits these
characteristics using data-parallel processing fed by a distributed memory
hierarchy managed by the compiler. The main challenge for next generation massively parallel processors is data bandwidth, not computational resources. Unlike most conventional processors, the technology does not rely on a hardware cache - instead data movement is explicitly mananged by the compiler and hardware.
The execution model is based on accelerating performance-critical functions (kernels) that process and
produce data records (streams). Kernels and streams are scheduled at compile-time and moved to on-chip memory at runtime via a scoreboard. The compiler analyses data live times
of streams to optimize allocation and minimize external memory bandwidth needs.
Streams and kernels loads can overlap with execution to improve latency
tolerance and the explicit data movement provides predictable performance. There
are no cache
misses and the design presents a single-core model to the
programmer – data-parallelism is within the kernels.
DSP Coprocessor Subsystem where the DSP MIPS runs the main threads that make
kernel function calls to the Data Parallel Unit (DPU). For users that use
libraries, and don’t intend to develop DSP code, the architecture is a
MIPS-based system-on-a-chip
with an API to a “black box”
coprocessor
. The DPU Dispatcher receives kernel function calls to manage
runtime kernel and stream loads. One kernel at a time is executed across the
lanes, operating on local stream data stored in the Lane Register File of each lane. Each
lane has a set of VLIW ALU
s and distributed operand register files (ORF)
allow for a large working data set and processing bandwidth exceeding 1 TeraByte/s. The Stream
Load/Store Unit provides gather/scatter with a wide variety of access patterns.
The InterLane Switch is a compiler
-scheduled, full crossbar for high-speed
access between lanes.
predictability of stream processing
to provide a fast path to optimized
results using C programming. Starting with C reference code, the Fast
Functional Debugger (FFD) library plugs into standard tools, such as Microsoft
Visual Studio and GNU, and simulates the DPU to support re-structuring code to
kernels and streams. Because kernels are statically scheduled and data movement
is explicit, DPU cycle-accuracy can be obtained even at this functional high
level. This is one source of the predictability of the architecture. For
targeting code to the device, the Stream Processor Compiler (SPC) generates the
VLIW executable and pre-processed C code that is compiled/linked via standard
GCC for MIPS. SPC allocates streams in the Lane Register Files and provides
dependency information for the kernel function calls. Software pipelining and
loop unrolling are supported. Branch penalties are avoided by predicated selects
and larger conditionals use conditional streams. Running under Eclipse, the
Target Code Simulator provides comprehensive Host or Device binary code
simulation with breakpoint and single-stepping capabilities with bandwidth and
load statistics. A kernel view shows the VLIW pipeline for kernel optimizations,
and a stream view shows kernel execution and stream loads to review global data
movement for system profiling.
Note: GMACS stands for Giga (billions of) Multiply-Accumulate operations per Second, a common measure of DSP
performance.
Silicon Valley
Silicon Valley is a term which refers to the southern part of the San Francisco Bay Area in Northern California in the United States. The region is home to many of the world's largest technology corporations...
-based fabless semiconductor company
Fabless semiconductor company
A fabless semiconductor company specializes in the design and sale of hardware devices and semiconductor chips while outsourcing the fabrication or "fab" of the devices to a specialized manufacturer called a semiconductor foundry...
specializing in the design and manufacture of high-performance digital signal processor
Digital signal processor
A digital signal processor is a specialized microprocessor with an architecture optimized for the fast operational needs of digital signal processing.-Typical characteristics:...
s for applications including video
surveillance, multi-function printers and video conferencing.
The company ceased operations in 2009.
Company history
Foundational work in stream processingStream processing
Stream processing is a computer programming paradigm, related to SIMD , that allows some applications to more easily exploit a limited form of parallel processing...
was initiated in
1995 by a research team led by MIT professor Bill Dally. In 1996, he moved to Stanford University
Stanford University
The Leland Stanford Junior University, commonly referred to as Stanford University or Stanford, is a private research university on an campus located near Palo Alto, California. It is situated in the northwestern Santa Clara Valley on the San Francisco Peninsula, approximately northwest of San...
where he continued this work, receiving a multi-million dollar
grant from DARPA with additional resources from Intel and
Texas Instruments
Texas Instruments
Texas Instruments Inc. , widely known as TI, is an American company based in Dallas, Texas, United States, which develops and commercializes semiconductor and computer technology...
to fund the development of a project called "Imagine"
- the first stream processor chip and accompanying compiler tools.
The Imagine Project
The goal of the Imagine project was to develop aC programmable signal and image processor intended to provide both the performance density and efficiency of a
special-purpose processor (such as a hard-wired ASIC
ASIC
ASIC may refer to:* Application-specific integrated circuit, an integrated circuit developed for a particular use, as opposed to a customised general-purpose device.* ASIC programming language, a dialect of BASIC...
). The project successfully demonstrated the advantages of stream processing. Details on the Imagine project and its results are posted
on the Stanford Imagine project page. The work also showed that a number of applications
ranging from wireless baseband processing, 3D graphics, encryption, IP
forwarding to video processing could take advantage of the efficiency of stream processing. This research inspired other
designs such as GPUs from ATI Technologies
ATI Technologies
ATI Technologies Inc. was a semiconductor technology corporation based in Markham, Ontario, Canada, that specialized in the development of graphics processing units and chipsets. Founded in 1985 as Array Technologies Inc., the company was listed publicly in 1993 and was acquired by Advanced Micro...
as well as the Cell microprocessor
Cell microprocessor
Cell is a microprocessor architecture jointly developed by Sony, Sony Computer Entertainment, Toshiba, and IBM, an alliance known as "STI". The architectural design and first implementation were carried out at the STI Design Center in Austin, Texas over a four-year period beginning March 2001 on a...
from Sony
Sony
, commonly referred to as Sony, is a Japanese multinational conglomerate corporation headquartered in Minato, Tokyo, Japan and the world's fifth largest media conglomerate measured by revenues....
, Toshiba
Toshiba
is a multinational electronics and electrical equipment corporation headquartered in Tokyo, Japan. It is a diversified manufacturer and marketer of electrical products, spanning information & communications equipment and systems, Internet-based solutions and services, electronic components and...
, and IBM
IBM
International Business Machines Corporation or IBM is an American multinational technology and consulting corporation headquartered in Armonk, New York, United States. IBM manufactures and sells computer hardware and software, and it offers infrastructure, hosting and consulting services in areas...
.
The main deliverables from the Imagine program included:
- The Imagine Stream Architecture
- The Stream programming model
- Software development tools
- Programmable graphics and real-time media applications
- VLSI prototype (fabricated by TI)
- Stream processor development platform (a prototype development board)
SPI established
Dally, together with other team members, obtained a license from Stanford to commercialize theresulting technology. Stream Processors, Incorporated (SPI) was incorporated in
California in 2004. Professor Dally remained at Stanford and the company
hired industry veteran Chip Stearns http://www.streamprocessors.com/streamprocessors/Home/About/PressReleases/2004-12-13.html to become the President and CEO in December of that
year. Through June, 2006 SPI has been able to raise a total of $26M from a trio of notable venture capital
Venture capital
Venture capital is financial capital provided to early-stage, high-potential, high risk, growth startup companies. The venture capital fund makes money by owning equity in the companies it invests in, which usually have a novel technology or business model in high technology industries, such as...
firms - Austin Ventures
Austin Ventures
Austin Ventures is a private equity firm focused on venture capital and growth equity investments in business services and supply chain, financial services, new media, Internet, and information services companies nationally with a focus on Texas. The firm, which is based in Austin, Texas, was...
, Norwest Venture Partners
Norwest venture partners
Norwest Venture Partners is a global, multi-stage investment firm focused on investments in early to late stage venture and growth equity investments in U.S...
and the Woodside Fund.
The company launched its first two products concurrently with the International Solid State
Circuits Conference (ISSCC) in February, 2006 and
has introduced two others since.
SPI has headquarters located in Sunnyvale, California
Sunnyvale, California
Sunnyvale is a city in Santa Clara County, California, United States. It is one of the major cities that make up the Silicon Valley located in the San Francisco Bay Area...
as well as a software development group (SPI Software Technologies Pvt. Ltd) located in Bangalore, India.
In January 2009 Co-Founder Prof. Bill Dally accepted a position as Chief Scientist with NVIDIA
NVIDIA
Nvidia is an American global technology company based in Santa Clara, California. Nvidia is best known for its graphics processors . Nvidia and chief rival AMD Graphics Techonologies have dominated the high performance GPU market, pushing other manufacturers to smaller, niche roles...
Corporation. At the same time he
resigned as chairman. In an interview Dally reflected on his experiences with startups:
" I have done several chip startups myself. It’s getting hard. The ante is very high. If you do a chip startup, you need patient investors with very deep pockets. It’s many tens of millions of dollars to get to a first product and $50 million to get to profits. That’s very difficult to do because investors want an exit some multiple over that investment. I am hoping we return to the days of frequent IPOs and get beyond the fire-sale acquisitions. That’s not what you can see right now. If it’s a programmable chip, the cost is even more."
In the summer of 2009 CEO Stearns left the company and was replaced by Mike Fister, an executive with senior level experience at Cadence Design Systems
Cadence Design Systems
Cadence Design Systems, Inc is an electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc...
and Intel.
In September 2009 the company ceased operations.
Technology
Similar to graphics and scientific computing, media and signal processingare characterized by available data-parallelism, locality and a high computation
to global memory access ratio. Stream processing
Stream processing
Stream processing is a computer programming paradigm, related to SIMD , that allows some applications to more easily exploit a limited form of parallel processing...
exploits these
characteristics using data-parallel processing fed by a distributed memory
hierarchy managed by the compiler. The main challenge for next generation massively parallel processors is data bandwidth, not computational resources. Unlike most conventional processors, the technology does not rely on a hardware cache - instead data movement is explicitly mananged by the compiler and hardware.
The execution model is based on accelerating performance-critical functions (kernels) that process and
produce data records (streams). Kernels and streams are scheduled at compile-time and moved to on-chip memory at runtime via a scoreboard. The compiler analyses data live times
of streams to optimize allocation and minimize external memory bandwidth needs.
Streams and kernels loads can overlap with execution to improve latency
tolerance and the explicit data movement provides predictable performance. There
are no cache
Cache
In computer engineering, a cache is a component that transparently stores data so that future requests for that data can be served faster. The data that is stored within a cache might be values that have been computed earlier or duplicates of original values that are stored elsewhere...
misses and the design presents a single-core model to the
programmer – data-parallelism is within the kernels.
Architecture
The architecture includes a host CPU (System MIPS) for system-level tasks and aDSP Coprocessor Subsystem where the DSP MIPS runs the main threads that make
kernel function calls to the Data Parallel Unit (DPU). For users that use
libraries, and don’t intend to develop DSP code, the architecture is a
MIPS-based system-on-a-chip
System-on-a-chip
A system on a chip or system on chip is an integrated circuit that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate...
with an API to a “black box”
coprocessor
Coprocessor
A coprocessor is a computer processor used to supplement the functions of the primary processor . Operations performed by the coprocessor may be floating point arithmetic, graphics, signal processing, string processing, or encryption. By offloading processor-intensive tasks from the main processor,...
. The DPU Dispatcher receives kernel function calls to manage
runtime kernel and stream loads. One kernel at a time is executed across the
lanes, operating on local stream data stored in the Lane Register File of each lane. Each
lane has a set of VLIW ALU
Arithmetic logic unit
In computing, an arithmetic logic unit is a digital circuit that performs arithmetic and logical operations.The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers...
s and distributed operand register files (ORF)
allow for a large working data set and processing bandwidth exceeding 1 TeraByte/s. The Stream
Load/Store Unit provides gather/scatter with a wide variety of access patterns.
The InterLane Switch is a compiler
Compiler
A compiler is a computer program that transforms source code written in a programming language into another computer language...
-scheduled, full crossbar for high-speed
access between lanes.
Tools
SPI’s RapiDev Tools Suite leverages thepredictability of stream processing
Stream processing
Stream processing is a computer programming paradigm, related to SIMD , that allows some applications to more easily exploit a limited form of parallel processing...
to provide a fast path to optimized
results using C programming. Starting with C reference code, the Fast
Functional Debugger (FFD) library plugs into standard tools, such as Microsoft
Visual Studio and GNU, and simulates the DPU to support re-structuring code to
kernels and streams. Because kernels are statically scheduled and data movement
is explicit, DPU cycle-accuracy can be obtained even at this functional high
level. This is one source of the predictability of the architecture. For
targeting code to the device, the Stream Processor Compiler (SPC) generates the
VLIW executable and pre-processed C code that is compiled/linked via standard
GCC for MIPS. SPC allocates streams in the Lane Register Files and provides
dependency information for the kernel function calls. Software pipelining and
loop unrolling are supported. Branch penalties are avoided by predicated selects
and larger conditionals use conditional streams. Running under Eclipse, the
Target Code Simulator provides comprehensive Host or Device binary code
simulation with breakpoint and single-stepping capabilities with bandwidth and
load statistics. A kernel view shows the VLIW pipeline for kernel optimizations,
and a stream view shows kernel execution and stream loads to review global data
movement for system profiling.
Products
SPI currently markets its Storm-1 family, that includes four fully software programmable DSPs of varying performance levels.| Product | GMACS* | Applications |
|---|---|---|
| SP16HP-G220 | 224 |
|
| SP16-G160 | 160 |
|
| SP8-G80 | 80 |
|
| SP8LP-G30 | 32 |
|
Note: GMACS stands for Giga (billions of) Multiply-Accumulate operations per Second, a common measure of DSP
performance.
Support hardware and software
- The RapiDev tools suite delivers a fast, predictable path to optimized results, eliminating the complexities of assembly coding or manual cache management
- The Storm-1 DevKit is a PCI-based software development platform
- IP Camera Reference Design runs standard Linux 2.6 and supports multiple simultaneous codecs (e.g. H.264, MPEG-4MPEG-4MPEG-4 is a method of defining compression of audio and visual digital data. It was introduced in late 1998 and designated a standard for a group of audio and video coding formats and related technology agreed upon by the ISO/IEC Moving Picture Experts Group under the formal standard ISO/IEC...
and MJPEGMJPEGIn multimedia, Motion JPEG is an informal name for a class of video formats where each video frame or interlaced field of a digital video sequence is separately compressed as a JPEG image...
), arbitrary resolutions, CMOSCMOSComplementary metal–oxide–semiconductor is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits...
and CCD sensor processing as well as video analytics in a fully software programmable platform - Video Streamer Reference Design supports eight 4CIF input channels of video compressed to H.264 and a Gigabit EthernetGigabit EthernetGigabit Ethernet is a term describing various technologies for transmitting Ethernet frames at a rate of a gigabit per second , as defined by the IEEE 802.3-2008 standard. It came into use beginning in 1999, gradually supplanting Fast Ethernet in wired local networks where it performed...
output