SuperH
Encyclopedia
SuperH is a 32-bit
reduced instruction set computer
(RISC) instruction set architecture (ISA) developed by Hitachi
. It is implemented by microcontroller
s and microprocessor
s for embedded system
s.
The SH-4 architecture supports both big-endian and little- endian byte ordering.
in the early 1990s.
Hitachi has developed a complete group of upward compatible instruction set CPU cores. The SH-1 and the SH-2 were used in the Sega Saturn
and Sega 32X
. These cores have 16-bit instructions for better code density than 32-bit instructions, a benefit at the time as memory was very expensive.
A few years later the SH-3 core was added to the SH CPU family; new features included another interrupt concept, a memory management unit
(MMU) and a modified cache concept. The SH-3 core also got a DSP
extension, then called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated MAC-type DSP engine, this core was unifying the DSP and the RISC processor world. A derivative was also used with the original SH-2 core.
For the Dreamcast, Hitachi
developed the SH-4 architecture. Superscalar
(2-way) instruction execution and a vector
floating point unit
were the highlights of this architecture. SH-4 based standard chips were introduced around 1998.
In early 2001, Hitachi
and ST Microelectronics formed the IP company
SuperH, Inc., which was going to license the SH-4 core to other companies and was developing the SH-5 architecture, the first move of SuperH into the 64-bit area. SuperH, Inc. sold the IP of these CPU cores to Renesas Technology in 2004.
The SH-5 design supported two modes of operation. SHcompact mode is equivalent to the user-mode instructions of the SH-4 instruction set. SHmedia mode is very different, using 32-bit instructions with sixty-four 64-bit integer registers and SIMD
instructions. In SHmedia mode the destination of a branch
(jump) is loaded into a branch register separately from the actual branch instruction. This allows the processor to prefetch instructions for a branch without having to snoop the instruction stream. The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5; ARM
processors have a 16-bit Thumb mode, and MIPS
processors have a MIPS-16 mode. However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather than the 32-bit encoding.
The evolution of the SuperH architecture still continues. The latest evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting unified into a superscalar SH-X core which forms a kind of instruction set superset of the previous architectures.
Today, the SuperH CPU cores, architecture and products are with Renesas Technology, a merger of the Hitachi and Mitsubishi semiconductor groups and the architecture is consolidated around the SH-2, SH-2A, SH-3, SH4 and SH-4A platforms giving a scalable family.
The family of SuperH CPU cores includes:
The SH-2 is a 32-bit RISC architecture, it has 16 general purpose registers, which makes it well suited for programs written in C
.
It has a 16-bit fixed length instructions for high code density, features a hardware multiply–accumulate (MAC) block for DSP algorithms and has a five-stage pipeline.
The SH-2 has a cache on all ROM-less devices.
It also provides a vector-base-register, global-base-register and a procedure register.
Today the SH-2 family stretches from 32k of on board flash up to ROM-less devices. It is used in a variety of different devices with differing peripherals such as CAN, Ethernet, motor-control timer unit, fast ADC and others.
At launch in 2007 the SH-2A based SH7211 was the world's fastest embedded flash microcontroller running at 160 MHz. It has later been superseded by several newer SuperH devices running at up to 200 MHz.
New features on the SH-2A core include:
The SH-2A family today spans a wide memory field from 16kB up to and includes many ROM
-less variations. The devices feature standard peripherals such as CAN, Ethernet
, USB and more as well as more application specific peripherals such as motor control
timers, TFT
controllers and peripherals dedicated to automotive powertrain applications.
SH-4 features include:
32-bit
The range of integer values that can be stored in 32 bits is 0 through 4,294,967,295. Hence, a processor with 32-bit memory addresses can directly access 4 GB of byte-addressable memory....
reduced instruction set computer
Reduced instruction set computer
Reduced instruction set computing, or RISC , is a CPU design strategy based on the insight that simplified instructions can provide higher performance if this simplicity enables much faster execution of each instruction. A computer based on this strategy is a reduced instruction set computer...
(RISC) instruction set architecture (ISA) developed by Hitachi
Hitachi
Hitachi is a multinational corporation specializing in high-technology.Hitachi may also refer to:*Hitachi, Ibaraki, Japan*Hitachi province, former province of Japan*Prince Hitachi and Princess Hitachi, members of the Japanese imperial family...
. It is implemented by microcontroller
Microcontroller
A microcontroller is a small computer on a single integrated circuit containing a processor core, memory, and programmable input/output peripherals. Program memory in the form of NOR flash or OTP ROM is also often included on chip, as well as a typically small amount of RAM...
s and microprocessor
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
s for embedded system
Embedded system
An embedded system is a computer system designed for specific control functions within a larger system. often with real-time computing constraints. It is embedded as part of a complete device often including hardware and mechanical parts. By contrast, a general-purpose computer, such as a personal...
s.
The SH-4 architecture supports both big-endian and little- endian byte ordering.
History
The SuperH processor core family was first developed by HitachiHitachi, Ltd.
is a Japanese multinational conglomerate headquartered in Marunouchi 1-chome, Chiyoda, Tokyo, Japan. The company is the parent of the Hitachi Group as part of the larger DKB Group companies...
in the early 1990s.
Hitachi has developed a complete group of upward compatible instruction set CPU cores. The SH-1 and the SH-2 were used in the Sega Saturn
Sega Saturn
The is a 32-bit fifth-generation video game console that was first released by Sega on November 22, 1994 in Japan, May 11, 1995 in North America, and July 8, 1995 in Europe...
and Sega 32X
Sega 32X
The Sega 32X, codenamed Project Mars, is an add-on for the Mega Drive/Genesis video game console by Sega. Its aim was to increase the lifespan of the aging Mega Drive/Genesis system, which was facing stiff competition from the SNES...
. These cores have 16-bit instructions for better code density than 32-bit instructions, a benefit at the time as memory was very expensive.
A few years later the SH-3 core was added to the SH CPU family; new features included another interrupt concept, a memory management unit
Memory management unit
A memory management unit , sometimes called paged memory management unit , is a computer hardware component responsible for handling accesses to memory requested by the CPU...
(MMU) and a modified cache concept. The SH-3 core also got a DSP
Digital signal processing
Digital signal processing is concerned with the representation of discrete time signals by a sequence of numbers or symbols and the processing of these signals. Digital signal processing and analog signal processing are subfields of signal processing...
extension, then called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated MAC-type DSP engine, this core was unifying the DSP and the RISC processor world. A derivative was also used with the original SH-2 core.
For the Dreamcast, Hitachi
Hitachi, Ltd.
is a Japanese multinational conglomerate headquartered in Marunouchi 1-chome, Chiyoda, Tokyo, Japan. The company is the parent of the Hitachi Group as part of the larger DKB Group companies...
developed the SH-4 architecture. Superscalar
Superscalar
A superscalar CPU architecture implements a form of parallelism called instruction level parallelism within a single processor. It therefore allows faster CPU throughput than would otherwise be possible at a given clock rate...
(2-way) instruction execution and a vector
Vector processor
A vector processor, or array processor, is a central processing unit that implements an instruction set containing instructions that operate on one-dimensional arrays of data called vectors. This is in contrast to a scalar processor, whose instructions operate on single data items...
floating point unit
Floating point unit
A floating-point unit is a part of a computer system specially designed to carry out operations on floating point numbers. Typical operations are addition, subtraction, multiplication, division, and square root...
were the highlights of this architecture. SH-4 based standard chips were introduced around 1998.
In early 2001, Hitachi
Hitachi, Ltd.
is a Japanese multinational conglomerate headquartered in Marunouchi 1-chome, Chiyoda, Tokyo, Japan. The company is the parent of the Hitachi Group as part of the larger DKB Group companies...
and ST Microelectronics formed the IP company
Patent holding company
Patent holding companies are companies set up to administer, consolidate and license patents or otherwise enforce patent rights, such as through litigation...
SuperH, Inc., which was going to license the SH-4 core to other companies and was developing the SH-5 architecture, the first move of SuperH into the 64-bit area. SuperH, Inc. sold the IP of these CPU cores to Renesas Technology in 2004.
The SH-5 design supported two modes of operation. SHcompact mode is equivalent to the user-mode instructions of the SH-4 instruction set. SHmedia mode is very different, using 32-bit instructions with sixty-four 64-bit integer registers and SIMD
SIMD
Single instruction, multiple data , is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data simultaneously...
instructions. In SHmedia mode the destination of a branch
Branch (computer science)
A branch is sequence of code in a computer program which is conditionally executed depending on whether the flow of control is altered or not . The term can be used when referring to programs in high level languages as well as program written in machine code or assembly language...
(jump) is loaded into a branch register separately from the actual branch instruction. This allows the processor to prefetch instructions for a branch without having to snoop the instruction stream. The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5; ARM
ARM architecture
ARM is a 32-bit reduced instruction set computer instruction set architecture developed by ARM Holdings. It was named the Advanced RISC Machine, and before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in numbers produced...
processors have a 16-bit Thumb mode, and MIPS
MIPS architecture
MIPS is a reduced instruction set computer instruction set architecture developed by MIPS Technologies . The early MIPS architectures were 32-bit, and later versions were 64-bit...
processors have a MIPS-16 mode. However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather than the 32-bit encoding.
The evolution of the SuperH architecture still continues. The latest evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting unified into a superscalar SH-X core which forms a kind of instruction set superset of the previous architectures.
Today, the SuperH CPU cores, architecture and products are with Renesas Technology, a merger of the Hitachi and Mitsubishi semiconductor groups and the architecture is consolidated around the SH-2, SH-2A, SH-3, SH4 and SH-4A platforms giving a scalable family.
Models
- SH-1 - used in microcontrollers for deeply embedded applications (CD-ROMCD-ROMA CD-ROM is a pre-pressed compact disc that contains data accessible to, but not writable by, a computer for data storage and music playback. The 1985 “Yellow Book” standard developed by Sony and Philips adapted the format to hold any form of binary data....
drives, major applianceMajor applianceA major appliance, or domestic appliance, is usually defined as a large machine which accomplishes some routine housekeeping task, which includes purposes such as cooking, or food preservation, whether in a household, institutional, commercial or industrial setting...
s, etc.) - SH-2 - used in microcontrollers with higher performance requirements, also used in automotive such as engine control unitEngine Control UnitAn engine control unit is a type of electronic control unit that determines the amount of fuel, ignition timing and other parameters an internal combustion engine needs to keep running...
s or in networking applications, and also in video game consoles, like the Sega Saturn. The SH-2 has also found home in many motor control applications. - SH-2A - The SH-2A core is an extension of the SH-2 core including a few extra instructions but most importantly moving to a superscalar architecture (it is capable of executing more than one instruction in a single cycle) and two five-stage pipelines. It also incorporates 15 register banks to facilitate an interrupt latency of 6 clock cycles. It is also strong in motor control application but also in multimedia, car audio, powertrain, automotive body control and office + building automation
- SH-DSP - initially developed for the mobile phoneMobile phoneA mobile phone is a device which can make and receive telephone calls over a radio link whilst moving around a wide geographic area. It does so by connecting to a cellular network provided by a mobile network operator...
market, used later in many consumer applications requiring DSP performance for JPEGJPEGIn computing, JPEG . The degree of compression can be adjusted, allowing a selectable tradeoff between storage size and image quality. JPEG typically achieves 10:1 compression with little perceptible loss in image quality....
compression etc. - SH-3 - used for mobile and handheld applications such as the Jornada, strong in Windows CEWindows CEMicrosoft Windows CE is an operating system developed by Microsoft for embedded systems. Windows CE is a distinct operating system and kernel, rather than a trimmed-down version of desktop Windows...
applications and market for many years in the car navigation market - SH-3-DSP - used mainly in multimedia terminals and networking applications, also in printers and fax machines
- SH-4 - used whenever high performance is required such as car multimedia terminals, video game consoleVideo game consoleA video game console is an interactive entertainment computer or customized computer system that produces a video display signal which can be used with a display device to display a video game...
s, or set-top boxSet-top boxA set-top box or set-top unit is an information appliance device that generally contains a tuner and connects to a television set and an external source of signal, turning the signal into content which is then displayed on the television screen or other display device.-History:Before the...
es - SH-5 - used in high-end multimedia applications
- SH-X - mainstream core used in various flavours (with/without DSP or FPU unit) in engine control unit, car multimedia equipment, set-top boxes or mobile phones
- SH-Mobile - SuperH Mobile Application Processor; designed to offload application processing from the baseband LSI
SH-2
C (programming language)
C is a general-purpose computer programming language developed between 1969 and 1973 by Dennis Ritchie at the Bell Telephone Laboratories for use with the Unix operating system....
.
It has a 16-bit fixed length instructions for high code density, features a hardware multiply–accumulate (MAC) block for DSP algorithms and has a five-stage pipeline.
The SH-2 has a cache on all ROM-less devices.
It also provides a vector-base-register, global-base-register and a procedure register.
Today the SH-2 family stretches from 32k of on board flash up to ROM-less devices. It is used in a variety of different devices with differing peripherals such as CAN, Ethernet, motor-control timer unit, fast ADC and others.
SH-2A
The SH-2A is an upgrade to the SH-2 core. It was announced in early 2006.At launch in 2007 the SH-2A based SH7211 was the world's fastest embedded flash microcontroller running at 160 MHz. It has later been superseded by several newer SuperH devices running at up to 200 MHz.
New features on the SH-2A core include:
- Superscalar architecture: execution of 2 instructions simultaneously.
- Harvard architectureHarvard architectureThe Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. The term originated from the Harvard Mark I relay-based computer, which stored instructions on punched tape and data in electro-mechanical counters...
- Two 5-stage pipelines.
- 15 register banks for interrupt response in 6 cycles.
- Optional FPU
The SH-2A family today spans a wide memory field from 16kB up to and includes many ROM
Read-only memory
Read-only memory is a class of storage medium used in computers and other electronic devices. Data stored in ROM cannot be modified, or can be modified only slowly or with difficulty, so it is mainly used to distribute firmware .In its strictest sense, ROM refers only...
-less variations. The devices feature standard peripherals such as CAN, Ethernet
Ethernet
Ethernet is a family of computer networking technologies for local area networks commercially introduced in 1980. Standardized in IEEE 802.3, Ethernet has largely replaced competing wired LAN technologies....
, USB and more as well as more application specific peripherals such as motor control
Motor control
Motor control are information processing related activities carried out by the central nervous system that organize the musculoskeletal system to create coordinated movements and skilled actions...
timers, TFT
Thin-film transistor
A thin-film transistor is a special kind of field-effect transistor made by depositing thin films of a semiconductor active layer as well as the dielectric layer and metallic contacts over a supporting substrate. A common substrate is glass, since the primary application of TFTs is in liquid...
controllers and peripherals dedicated to automotive powertrain applications.
SH-4
The SH-4 was developed for primary use in multimedia applications, such as Sega's Dreamcast and NAOMI game systems. It includes a much more powerful floating point unit and additional built-in functions, along with the standard 32-bit integer processing and 16-bit instruction size.SH-4 features include:
- FPU with four floating point multipliers, supporting 32-bit single precision and 64-bit double precision floats
- 128-bit floating point bus allowing 3.2GB/sec transfer rate from the data cache
- 64-bit external data bus with 32-bit memory addressing, allowing a maximum of 4GB addressable memory with a transfer rate of 800MB/sec
- Built-in interrupt, DMA, and power management controllers