System Packet Interface
Encyclopedia
The System Packet Interface family of Interoperability Agreements from the Optical Internetworking Forum
specify chip-to-chip, channelized, packet interfaces commonly used in synchronous optical networking
and ethernet
applications. A typical application of such a packet level interface is between a framer (for optical network) or a MAC (for IP network) and a network processor. Another application of this interface might be between a packet processor ASIC
and a traffic manager device.
, supports reads and writes of memory addresses. The second broad category carries user packets over 1 or more channels and is exemplified by the IEEE 802.3
family of Media Independent Interface
s and the Optical Internetworking Forum
family of System Packet Interfaces. Of these last two, the family of System Packet Interfaces is optimized to carry user packets from many channels. The family of System Packet Interfaces is the most important packet-oriented, chip-to-chip interface family used between devices in the Packet over SONET and Optical Transport Network
, which are the principal protocols used to carry the internet between cities.
The term SPI may also refer to a set of low-rate serial communications protocols, not related to optical communications, usually used for transferring data between devices on a printed circuit board; more information may be found here: Serial Peripheral Interface.
and PL-4
which themselves came from the ATM Forum
's Utopia definitions which had included:
System Packet Interface or SPI as it is widely known is a protocol for packet and cell transfers between PHY and LINK layer devices in multi-gigabit applications. This protocol has been developed by Optical Internetworking Forum (OIF) and is fast emerging as one of the most important integration standards in the history of telecommunications and data networking. Devices implementing SPI are typically specified with line rates of 700~800 Mbit/s and in some cases up to 1 Gbit/s. The latest version is SPI 4 Phase 2 also known as SPI 4.2 delivers bandwidth of up to 16 Gbit/s for a 16 bit interface.
Example:
GigEth---SPI----Network Processor
To ensure optimal use of the rx/tx buffers in devices connected with SPI interface, the RBUF/TBUF element size in those devices should match the SPI-4.2 data burst size.
Optical Internetworking Forum
The Optical Internetworking Forum is a non-profit, member-driven organization founded in 1998. It promotes the development and deployment of interoperable networking solutions and services through the creation of Implementation Agreements for optical networking products, network processing...
specify chip-to-chip, channelized, packet interfaces commonly used in synchronous optical networking
Synchronous optical networking
Synchronous Optical Networking and Synchronous Digital Hierarchy are standardized multiplexing protocols that transfer multiple digital bit streams over optical fiber using lasers or highly coherent light from light-emitting diodes . At low transmission rates data can also be transferred via an...
and ethernet
Ethernet
Ethernet is a family of computer networking technologies for local area networks commercially introduced in 1980. Standardized in IEEE 802.3, Ethernet has largely replaced competing wired LAN technologies....
applications. A typical application of such a packet level interface is between a framer (for optical network) or a MAC (for IP network) and a network processor. Another application of this interface might be between a packet processor ASIC
Application-specific integrated circuit
An application-specific integrated circuit is an integrated circuit customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC...
and a traffic manager device.
Context
There are two broad categories of chip-to-chip interfaces. The first, exemplified by PCI-Express and HyperTransportHyperTransport
HyperTransport , formerly known as Lightning Data Transport , is a technology for interconnection of computer processors. It is a bidirectional serial/parallel high-bandwidth, low-latency point-to-point link that was introduced on April 2, 2001...
, supports reads and writes of memory addresses. The second broad category carries user packets over 1 or more channels and is exemplified by the IEEE 802.3
IEEE 802.3
IEEE 802.3 is a working group and a collection of IEEE standards produced by the working group defining the physical layer and data link layer's media access control of wired Ethernet. This is generally a local area network technology with some wide area network applications...
family of Media Independent Interface
Media Independent Interface
The Media Independent Interface was originally defined as a standard interface used to connect a Fast Ethernet MAC-block to a PHY chip.The MII design has been extended to support reduced signals and increases speeds...
s and the Optical Internetworking Forum
Optical Internetworking Forum
The Optical Internetworking Forum is a non-profit, member-driven organization founded in 1998. It promotes the development and deployment of interoperable networking solutions and services through the creation of Implementation Agreements for optical networking products, network processing...
family of System Packet Interfaces. Of these last two, the family of System Packet Interfaces is optimized to carry user packets from many channels. The family of System Packet Interfaces is the most important packet-oriented, chip-to-chip interface family used between devices in the Packet over SONET and Optical Transport Network
Optical Transport Network
ITU-T defines an Optical Transport Network as a set of Optical Network Elements connected by optical fibre links, able to provide functionality of transport, multiplexing, switching, management, supervision and survivability of optical channels carrying client signals...
, which are the principal protocols used to carry the internet between cities.
The term SPI may also refer to a set of low-rate serial communications protocols, not related to optical communications, usually used for transferring data between devices on a printed circuit board; more information may be found here: Serial Peripheral Interface.
Specifications
The agreements are:- SPI-3SPI-3SPI-3 or System Packet Interface Level 3 is the name of a chip-to-chip, channelized, packet interface widely used in high-speed communications devices. It was proposed by PMC-Sierra based on their PL-3 interface to the Optical Internetworking Forum and adopted in June of 2000...
– Packet Interface for Physical and Link Layers for OC-48 (2.488 Gbit/s) - SPI-4.1 – System Physical Interface Level 4 (SPI-4) Phase 1: A System Interface for Interconnection Between Physical and Link Layer, or Peer-to-Peer Entities Operating at an OC-192 Rate (10 Gbit/s).
- SPI-4.2SPI-4.2SPI-4.2 is a version of the System Packet Interface published by the Optical Internetworking Forum. It was designed to be used in systems that support OC-192 SONET interfaces and is sometimes used in 10 Gigabit Ethernet based systems....
– System Packet Interface Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and Link Layer Devices. - SPI-5 – Packet Interface for Physical and Link Layers for OC-768 (40 Gbit/s)
- SPI-S – Scalable System Packet Interface - useful for interfaces starting with OC-48 and scaling into the Terabit range
History of the specifications
These agreements grew out of the POS-PHY interface definitions PL-3PL-3
PL-3 or POS-PHY Level 3 was the name of the interface that the Optical Internetworking Forum's SPI-3 Interoperability Agreement is based on. It was proposed by PMC-Sierra to the Optical Internetworking Forum and adopted in June of 2000. The name means Packet Over SONET Physical layer level 3...
and PL-4
PL-4
PL-4 or POS-PHY Level 4 was the name of the interface that the interface SPI-4.2 is based on. It was proposed by PMC-Sierra to the Optical Internetworking Forum. The name means Packet Over SONET Physical layer level 4. PL-4 was developed by PMC-Sierra in conjunction with the Saturn Development...
which themselves came from the ATM Forum
ATM Forum
The ATM Forum was founded in 1991 to be the industry consortium to promote Asynchronous Transfer Mode technology used in telecommunication networks. It was a non-profit international organization. The ATM Forum created over 200 implementation agreements....
's Utopia definitions which had included:
- Utopia Level 1, an 8 bit, 25 MHz interface supporting OC-3 and slower links (or multiple links aggregating to less than 200 Mbit/s).
- Utopia Level 2, a 16 bit, 50 MHz interface supporting OC-12 or multiple links aggregating to less than 800 Mbit/s.
System Packet Interface or SPI as it is widely known is a protocol for packet and cell transfers between PHY and LINK layer devices in multi-gigabit applications. This protocol has been developed by Optical Internetworking Forum (OIF) and is fast emerging as one of the most important integration standards in the history of telecommunications and data networking. Devices implementing SPI are typically specified with line rates of 700~800 Mbit/s and in some cases up to 1 Gbit/s. The latest version is SPI 4 Phase 2 also known as SPI 4.2 delivers bandwidth of up to 16 Gbit/s for a 16 bit interface.
Applications
An example usage of SPI interface is in connecting Network Processors to PHY layer devices. ie. connecting the MSF of IXP2800 (LINK layer) with IXF framer (PHY layer).Example:
GigEth---SPI----Network Processor
SPI 4.2
The SPI 4.2 interface is composed of high speed clock, control, and data lines and lower speed FIFO buffer status lines. The high speed data line include a 16-bit data bus, a 1 bit control line and a double data rate (DDR) clock. The clock can run up to 500 MHz, supporting up to 1 GigaTransfer per second. The FIFO buffer status portion consists of a 2 bit status channel and a clock. SPI 4.2 supports a data width of 16 bits and can be PHY-link, link-link, link-PHY or PHY-PHY connection. The SPI 4.2 interface supports up to 256 port addresses with independent flow control for each.To ensure optimal use of the rx/tx buffers in devices connected with SPI interface, the RBUF/TBUF element size in those devices should match the SPI-4.2 data burst size.