Test compression
Encyclopedia
Test Compression is a technique used to reduce the time and cost of testing integrated circuit
s. The first ICs were tested with test vectors created by hand. It proved very difficult to get good coverage of potential faults, so Design for test
ability (DFT) based on scan and automatic test pattern generation
(ATPG) were developed to explicitly test each gate and path in a design. These techniques were very successful at creating high-quality vectors for manufacturing test, with excellent test coverage. However, as chips got bigger the ratio of logic to be tested per pin increased dramatically, and the volume of scan test data started causing a significant increase in test time, and required tester memory. This raised the cost of testing.
Test compression was developed to help address this problem. When an ATPG tool generates a test for a fault, or a set of faults, only a small percentage of scan cells need to take specific values. The rest of the scan chain is don't care, and are usually filled with random values. Loading and unloading these vectors is not a very efficient use of tester time. Test compression takes advantage of the small number of significant values to reduce test data and test time. In general, the idea is to modify the design to increase the number of internal scan chains, each of shorter length. These chains are then driven by an on-chip decompressor, usually designed to allow continuous flow decompression where the internal scan chains are loaded as the data is delivered to the decompressor. Many different decompression methods can be used. One common choice is a linear finite state machine, where the compressed stimuli are computed by solving linear equations corresponding to internal scan cells with specified positions in partially specified test patterns. Experimental results show that for industrial circuits with test vectors and responses with very low fill rates, ranging from 3% to 0.2%, the test compression based on this method often results in compression ratios of 30 to 500 times.
With a large number of test chains, not all the outputs can be sent to the output pins. Therefore, a test response compactor is also required, which must be inserted between the internal scan chain outputs and the tester scan channel outputs. The compactor must be synchronized with the date decompressor, and must be capable of handling unknown (X) states. (Even if the input is fully specified by the decompressor, these can result from false and multi-cycle paths, for example.) Another design criteria for the test result compressor is that it should give good diagnostic capabilities, not just a yes/no answer.
Integrated circuit
An integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...
s. The first ICs were tested with test vectors created by hand. It proved very difficult to get good coverage of potential faults, so Design for test
Design For Test
Design for Test is a name for design techniques that add certain testability features to a microelectronic hardware product design. The premise of the added features is that they make it easier to develop and apply manufacturing tests for the designed hardware...
ability (DFT) based on scan and automatic test pattern generation
Automatic test pattern generation
ATPG is an electronic design automation method/technology used to find an input sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit...
(ATPG) were developed to explicitly test each gate and path in a design. These techniques were very successful at creating high-quality vectors for manufacturing test, with excellent test coverage. However, as chips got bigger the ratio of logic to be tested per pin increased dramatically, and the volume of scan test data started causing a significant increase in test time, and required tester memory. This raised the cost of testing.
Test compression was developed to help address this problem. When an ATPG tool generates a test for a fault, or a set of faults, only a small percentage of scan cells need to take specific values. The rest of the scan chain is don't care, and are usually filled with random values. Loading and unloading these vectors is not a very efficient use of tester time. Test compression takes advantage of the small number of significant values to reduce test data and test time. In general, the idea is to modify the design to increase the number of internal scan chains, each of shorter length. These chains are then driven by an on-chip decompressor, usually designed to allow continuous flow decompression where the internal scan chains are loaded as the data is delivered to the decompressor. Many different decompression methods can be used. One common choice is a linear finite state machine, where the compressed stimuli are computed by solving linear equations corresponding to internal scan cells with specified positions in partially specified test patterns. Experimental results show that for industrial circuits with test vectors and responses with very low fill rates, ranging from 3% to 0.2%, the test compression based on this method often results in compression ratios of 30 to 500 times.
With a large number of test chains, not all the outputs can be sent to the output pins. Therefore, a test response compactor is also required, which must be inserted between the internal scan chain outputs and the tester scan channel outputs. The compactor must be synchronized with the date decompressor, and must be capable of handling unknown (X) states. (Even if the input is fully specified by the decompressor, these can result from false and multi-cycle paths, for example.) Another design criteria for the test result compressor is that it should give good diagnostic capabilities, not just a yes/no answer.
See also
- Design For TestDesign For TestDesign for Test is a name for design techniques that add certain testability features to a microelectronic hardware product design. The premise of the added features is that they make it easier to develop and apply manufacturing tests for the designed hardware...
- Automatic test pattern generationAutomatic test pattern generationATPG is an electronic design automation method/technology used to find an input sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit...
- Electronic design automationElectronic design automationElectronic design automation is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits...
- Integrated circuit designIntegrated circuit designIntegrated circuit design, or IC design, is a subset of electrical engineering and computer engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs...
External links
- Abstract and video of an IEEE lecture on test compression sponsored by the IEEE Council on Electronic Design AutomationIEEE Council on Electronic Design AutomationThe IEEE Council on Electronic Design Automation, also called IEEE CEDA, or Council on EDA, or just CEDA, is an organizational unit of the IEEE. It was started since many of the member societies have a common interest in electronic design automation, or EDA...
. This article was compiled from ideas covered in this lecture.