Unibus
Encyclopedia
The Unibus was the earliest of several computer bus
technologies used with PDP-11
and early VAX
systems manufactured by the Digital Equipment Corporation
(DEC) of Maynard
, Massachusetts
.
and student Harold McFarland while at Carnegie Mellon University
.
The Unibus was composed of 72 wires (2 connectors x 36 lines per connector). When not counting the power and ground lines, it is usually referred to as a 56 line bus. It could exist within a backplane or on a cable. Up to 20 nodes (devices) could be connected to a single Unibus segment; additional segments could be connected via a bus repeater
.
The bus was completely asynchronous, allowing a mixture of fast and slow devices. It allowed the overlapping of arbitration (selection of the next bus master) while the current bus master was still performing data transfers. The 18 address lines allowed the addressing of a maximum of 256 kB
. Typically, the top 8 kB was reserved for the registers of the memory-mapped I/O
devices used in the PDP-11 architecture.
The design deliberately minimized the amount of redundant logic required in the system. For example, a system always contained more slave devices than master devices so most of the fancy logic required to implement asynchronous data transfers was forced into the relatively few master devices. For interrupts, only the interrupt-fielding processor needed to contain the complicated timing logic. The end result was that most I/O controllers could be implemented with very simple logic and most of the critical logic was implemented as a custom MSI IC.
18 A00-A17 - Address Lines
16 D00-D15 - Data Lines
4 BR4-BR7 - Bus (Interrupt) Requests at priorities 4 (lowest) through 7 (highest)
4 BG4-BG7 - Bus (Interrupt) Grants at priorities 4 (lowest) through 7 (highest)
1 NPR - Non Processor (DMA) Request
1 NPG - Non Processor (DMA) Grant
1 ACLO - AC Low
1 DCLO - DC Low
1 MSYNC - Master Sync
1 SSYNC - Slave Sync
1 BBSY - Bus Busy
1 SACK - Selection Acknowledge
1 INIT - Bus Init
1 INTR - Interrupt Request
1 PA - Parity control
1 PB - Parity control
2 C0-C1 - Cyce Control Lines:
2 +5v - Power Lines (not counted as part of the 56)
14 Gnd - Ground Lines (not counted as part of the 56)
The two control lines (C0 and C1) allowed the selection of four different data transfer cycles:
Computer bus
In computer architecture, a bus is a subsystem that transfers data between components inside a computer, or between computers.Early computer buses were literally parallel electrical wires with multiple connections, but the term is now used for any physical arrangement that provides the same...
technologies used with PDP-11
PDP-11
The PDP-11 was a series of 16-bit minicomputers sold by Digital Equipment Corporation from 1970 into the 1990s, one of a succession of products in the PDP series. The PDP-11 replaced the PDP-8 in many real-time applications, although both product lines lived in parallel for more than 10 years...
and early VAX
VAX
VAX was an instruction set architecture developed by Digital Equipment Corporation in the mid-1970s. A 32-bit complex instruction set computer ISA, it was designed to extend or replace DEC's various Programmed Data Processor ISAs...
systems manufactured by the Digital Equipment Corporation
Digital Equipment Corporation
Digital Equipment Corporation was a major American company in the computer industry and a leading vendor of computer systems, software and peripherals from the 1960s to the 1990s...
(DEC) of Maynard
Maynard, Massachusetts
Maynard is a town in Middlesex County, Massachusetts, United States. As of the 2010 census, the town population was 10,106.- History :Maynard, located on the Assabet River, was incorporated as an independent municipality in 1871. Prior to that it was known as 'Assabet Village' but was legally...
, Massachusetts
Massachusetts
The Commonwealth of Massachusetts is a state in the New England region of the northeastern United States of America. It is bordered by Rhode Island and Connecticut to the south, New York to the west, and Vermont and New Hampshire to the north; at its east lies the Atlantic Ocean. As of the 2010...
.
History
The Unibus was developed around 1969 by Gordon BellGordon Bell
C. Gordon Bell is an American computer engineer and manager. An early employee of Digital Equipment Corporation 1960–1966, Bell designed several of their PDP machines and later became Vice President of Engineering 1972-1983, overseeing the development of the VAX...
and student Harold McFarland while at Carnegie Mellon University
Carnegie Mellon University
Carnegie Mellon University is a private research university in Pittsburgh, Pennsylvania, United States....
.
The Unibus was composed of 72 wires (2 connectors x 36 lines per connector). When not counting the power and ground lines, it is usually referred to as a 56 line bus. It could exist within a backplane or on a cable. Up to 20 nodes (devices) could be connected to a single Unibus segment; additional segments could be connected via a bus repeater
Repeater
A repeater is an electronic device that receives asignal and retransmits it at a higher level and/or higher power, or onto the other side of an obstruction, so that the signal can cover longer distances.-Description:...
.
The bus was completely asynchronous, allowing a mixture of fast and slow devices. It allowed the overlapping of arbitration (selection of the next bus master) while the current bus master was still performing data transfers. The 18 address lines allowed the addressing of a maximum of 256 kB
Kilobyte
The kilobyte is a multiple of the unit byte for digital information. Although the prefix kilo- means 1000, the term kilobyte and symbol KB have historically been used to refer to either 1024 bytes or 1000 bytes, dependent upon context, in the fields of computer science and information...
. Typically, the top 8 kB was reserved for the registers of the memory-mapped I/O
Memory-mapped I/O
Memory-mapped I/O and port I/O are two complementary methods of performing input/output between the CPU and peripheral devices in a computer...
devices used in the PDP-11 architecture.
The design deliberately minimized the amount of redundant logic required in the system. For example, a system always contained more slave devices than master devices so most of the fancy logic required to implement asynchronous data transfers was forced into the relatively few master devices. For interrupts, only the interrupt-fielding processor needed to contain the complicated timing logic. The end result was that most I/O controllers could be implemented with very simple logic and most of the critical logic was implemented as a custom MSI IC.
18 A00-A17 - Address Lines
16 D00-D15 - Data Lines
4 BR4-BR7 - Bus (Interrupt) Requests at priorities 4 (lowest) through 7 (highest)
4 BG4-BG7 - Bus (Interrupt) Grants at priorities 4 (lowest) through 7 (highest)
1 NPR - Non Processor (DMA) Request
1 NPG - Non Processor (DMA) Grant
1 ACLO - AC Low
1 DCLO - DC Low
1 MSYNC - Master Sync
1 SSYNC - Slave Sync
1 BBSY - Bus Busy
1 SACK - Selection Acknowledge
1 INIT - Bus Init
1 INTR - Interrupt Request
1 PA - Parity control
1 PB - Parity control
2 C0-C1 - Cyce Control Lines:
2 +5v - Power Lines (not counted as part of the 56)
14 Gnd - Ground Lines (not counted as part of the 56)
The two control lines (C0 and C1) allowed the selection of four different data transfer cycles:
- DATI (Data In, a read)
- DATIP (Data In/Pause, the first portion of a Read-Modify-Write operation. A DATO or DATOB operation completes this.)
- DATO (Data Out, a word write)
- DATOB (Data Out/Byte, a byte write)
- During an interrupt cycle, a fifth style of transfer was automatically invoked to convey an interrupt vector from the interrupting device to the interrupt-fielding processor.