Universal Verification Methodology
Encyclopedia
The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit
designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM
(e Reuse Methodology) for the e Verification Language
developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys.
— a standards organization in the electronic design automation
(EDA) industry — voted to establish the UVM and decided to base this new standard on the Open Verification Methodology (OVM-2.1.1), a verification methodology developed jointly in 2007 by Cadence Design Systems
and Mentor Graphics
.
On February 21, 2011, Accellera approved the 1.0 version of UVM. UVM 1.0 includes a Reference Guide, a Reference Implementation in the form of a SystemVerilog
base class library, and a User Guide..
Integrated circuit
An integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...
designs. UVM is derived mainly from the OVM (Open Verification Methodology) which was, to a large part, based on the eRM
ERM (e Reuse Methodology)
The e Reuse Methodology was the first reuse methodology to emerge in the Hardware Verification Language space and was used in conjunction with the e Hardware Verification Language. It was invented in 2001 by Verisity Design and was released in 2002...
(e Reuse Methodology) for the e Verification Language
E (verification language)
e is a hardware verification language which is tailored to implementing highly flexible and reusable verification testbenches.- History :...
developed by Verisity Design in 2001. The UVM class library brings much automation to the SystemVerilog language such as sequences and data automation features (packing, copy, compare) etc., and unlike the previous methodologies developed independently by the simulator vendors, is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor, and Synopsys.
History
In December 2009, a technical subcommittee of AccelleraAccellera
Accellera is a standards organization that supports a mix of user and vendor standards and open interfaces development in the area of electronic design automation and IC design and manufacturing. It is less constrained than the IEEE and is therefore the starting place for many standards. Once...
— a standards organization in the electronic design automation
Electronic design automation
Electronic design automation is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits...
(EDA) industry — voted to establish the UVM and decided to base this new standard on the Open Verification Methodology (OVM-2.1.1), a verification methodology developed jointly in 2007 by Cadence Design Systems
Cadence Design Systems
Cadence Design Systems, Inc is an electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc...
and Mentor Graphics
Mentor Graphics
Mentor Graphics, Inc is a US-based multinational corporation dealing in electronic design automation for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create...
.
On February 21, 2011, Accellera approved the 1.0 version of UVM. UVM 1.0 includes a Reference Guide, a Reference Implementation in the form of a SystemVerilog
SystemVerilog
In the semiconductor and electronic design industry, SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog.-History:...
base class library, and a User Guide..