VIA C3
Encyclopedia
The VIA C3 is a family of x86 central processing unit
s for personal computer
s designed by Centaur Technology
and sold by VIA Technologies
. The different CPU cores are built following the design methodology of Centaur Technology.
was renamed VIA C3 with the switch to the advanced "Samuel 2" (C5B) core. The addition of an on-die L2 cache
improved performance somewhat. As it was not built upon Cyrix
technology at all, the new name was just a logical step. To improve power consumption and reduce manufacturing costs, Samuel 2 was produced with 150 nm process technology.
The VIA C3 processor continued an emphasis on minimizing power consumption with the next die shrink to a mixed 130/150 nm process. "Ezra" (C5C) and "Ezra-T" (C5N) were only new revisions of the "Samuel 2" core with some minor modifications to the bus protocol of "Ezra-T" to match compatibility with Intel's Pentium III "Tualatin" cores. VIA enjoyed the lowest power usage in the x86 CPU market for several years. Performance, however, fell behind due to the lack of improvements to the design.
Uniquely, the retail C3 CPU shipped inside a metal package.
. The number of pipeline stages was increased from 12 to 16, to allow for continued increases in clock speed. Additionally, it implemented the cmov instruction, making it a 686-class processor. The Linux kernel refers to this core as the C3-2. It also removes 3DNow!
instructions in favour of implementing SSE
. However, it was still based upon the aging Socket 370
, running the single data rate front side bus
at just 133 MHz.
Because the embedded system marketplace prefers low-power, low-cost CPU designs, VIA began targeting this segment more aggressively because the C3 fit those traits rather well. Centaur Technology concentrated on adding features attractive to the embedded marketplace. An example built into the first "Nehemiah" (C5XL) core were the twin hardware random number generator
s. (These generators are erroneously called “quantum-based” in VIA's marketing literature. Detailed analysis of the generator makes it clear that the source of randomness is thermal, not quantum.)
The "C5P" revision of "Nehemiah" brought with it a few more advancements, including a high-performance AES
encryption engine along with a notably small ball grid array
chip package the size of a US 1 cent coin
.
When this architecture was marketed it was often referred to as the "VIA C5".
! style="text-align: center; background: #ccccff;"|Processor
! style="text-align: center; background: #ccccff;"|Secondary
Cache (KiB)
! style="text-align: center; background: #ccccff;"|Die size
180 nm (mm²)
! style="text-align: center; background: #ccccff;"|Die size
150 nm (mm²)
! style="text-align: center; background: #ccccff;"|Die size
130 nm (mm²)
! style="text-align: center; background: #ccccff;"|Die size
90 nm (mm²)
|- align="center"
! C3 Samuel
| N/A || ? || N/A || N/A || N/A
|- align="center"
! C3 Samuel 2
| 64 || N/A || ? || N/A || N/A
|- align="center"
! C3 Ezra
| 64 || N/A || N/A || 52 || N/A
|- align="center"
! C3 Nehemiah
| 64 || N/A || N/A || 52 || N/A
|- align="center"
! C7 Esther
| 128 || N/A || N/A || N/A || 30
|- align="center"
! Athlon XP
| 256 || N/A || N/A || 84 || N/A
|- align="center"
! Athlon 64
| 512 || N/A || N/A || 144 || 84
|- align="center"
! Pentium M
| 2048 || N/A || N/A || N/A || 84
|- align="center"
! P4 Northwood
| 512 || N/A || N/A || 146 || N/A
|- align="center"
! P4 Prescott
| 1024 || N/A || N/A || N/A || 110
, and evolutionary architecture changes from the Nehemiah.
While slower than x86 CPUs being sold by AMD and Intel, both in absolute terms and on a clock for clock basis, VIA's chips are much smaller, cheaper to manufacture, and lower power. This makes them highly attractive in the embedded marketplace, and increasingly in the mobile sector as well.
This has also enabled VIA to continue to scale the frequencies of their chips with each manufacturing process die shrink, while competitive products from Intel (such as the P4 Prescott) have encountered severe thermal management issues, although the new Intel Core
generation of chips are substantially cooler.
To this extent, the performance gap that used to exist between VIA and competing x86 chips is still wide, but starting to narrow. Some of the design trade offs made by the VIA design team are worthy of study, as they run contrary to accepted wisdom.
, Murano
, and Presage
. These and other high volume industrial applications are starting to generate big profits for VIA as the small form factor and low power advantages close embedded deals.
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
s for personal computer
Personal computer
A personal computer is any general-purpose computer whose size, capabilities, and original sales price make it useful for individuals, and which is intended to be operated directly by an end-user with no intervening computer operator...
s designed by Centaur Technology
Centaur Technology
Centaur Technology is an x86 CPU design company, now a wholly owned subsidiary of VIA Technologies, a member of the Formosa Plastics Group, Taiwan's largest industrial conglomerate.-History:...
and sold by VIA Technologies
VIA Technologies
VIA Technologies is a Taiwanese manufacturer of integrated circuits, mainly motherboard chipsets, CPUs, and memory, and is part of the Formosa Plastics Group. It is the world's largest independent manufacturer of motherboard chipsets...
. The different CPU cores are built following the design methodology of Centaur Technology.
Samuel 2 and Ezra cores
VIA Cyrix IIICyrix III
Cyrix III is an x86-compatible Socket 370 CPU. VIA Technologies launched the processor in February 2000. VIA had recently purchased both Centaur Technology and Cyrix. Cyrix III was to be based upon a core from one of the two companies.- Joshua :...
was renamed VIA C3 with the switch to the advanced "Samuel 2" (C5B) core. The addition of an on-die L2 cache
CPU cache
A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations...
improved performance somewhat. As it was not built upon Cyrix
Cyrix
Cyrix Corporation was a microprocessor developer that was founded in 1988 in Richardson, Texas as a specialist supplier of high-performance math coprocessors for 286 and 386 microprocessors. The company was founded by former Texas Instruments staff members and had a long but troubled relationship...
technology at all, the new name was just a logical step. To improve power consumption and reduce manufacturing costs, Samuel 2 was produced with 150 nm process technology.
The VIA C3 processor continued an emphasis on minimizing power consumption with the next die shrink to a mixed 130/150 nm process. "Ezra" (C5C) and "Ezra-T" (C5N) were only new revisions of the "Samuel 2" core with some minor modifications to the bus protocol of "Ezra-T" to match compatibility with Intel's Pentium III "Tualatin" cores. VIA enjoyed the lowest power usage in the x86 CPU market for several years. Performance, however, fell behind due to the lack of improvements to the design.
Uniquely, the retail C3 CPU shipped inside a metal package.
Nehemiah cores
The "Nehemiah" (C5XL) was a major core revision. At the time, VIA's marketing efforts did not fully reflect the changes that had taken place. The company addressed numerous design shortcomings of the older cores, including incomplete MMX compatibility and the half-speed FPUFPU
FPU may stand for:* Federation of Progressive Unions, a trade union center in Mauritius* Federation of Trade Unions of Ukraine* Fishermen's Protective Union, a left populist political party and later service organization in the former Dominion of Newfoundland from 1908 to the 1960s* Floating-point...
. The number of pipeline stages was increased from 12 to 16, to allow for continued increases in clock speed. Additionally, it implemented the cmov instruction, making it a 686-class processor. The Linux kernel refers to this core as the C3-2. It also removes 3DNow!
3DNow!
3DNow! is an extension to the x86 instruction set developed by Advanced Micro Devices . It adds single instruction multiple data instructions to the base x86 instruction set, enabling it to perform simple vector processing, which improves the performance of many graphic-intensive applications...
instructions in favour of implementing SSE
Streaming SIMD Extensions
In computing, Streaming SIMD Extensions is a SIMD instruction set extension to the x86 architecture, designed by Intel and introduced in 1999 in their Pentium III series processors as a reply to AMD's 3DNow! . SSE contains 70 new instructions, most of which work on single precision floating point...
. However, it was still based upon the aging Socket 370
Socket 370
Socket 370 is a common format of CPU socket first used by Intel for Pentium III and Celeron processors to replace the older Slot 1 CPU interface on personal computers. The "370" refers to the number of pin holes in the socket for CPU pins...
, running the single data rate front side bus
Front side bus
A front-side bus is a computer communication interface often used in computers during the 1990s and 2000s.It typically carries data between the central processing unit and a memory controller hub, known as the northbridge....
at just 133 MHz.
Because the embedded system marketplace prefers low-power, low-cost CPU designs, VIA began targeting this segment more aggressively because the C3 fit those traits rather well. Centaur Technology concentrated on adding features attractive to the embedded marketplace. An example built into the first "Nehemiah" (C5XL) core were the twin hardware random number generator
Hardware random number generator
In computing, a hardware random number generator is an apparatus that generates random numbers from a physical process. Such devices are often based on microscopic phenomena that generate a low-level, statistically random "noise" signal, such as thermal noise or the photoelectric effect or other...
s. (These generators are erroneously called “quantum-based” in VIA's marketing literature. Detailed analysis of the generator makes it clear that the source of randomness is thermal, not quantum.)
The "C5P" revision of "Nehemiah" brought with it a few more advancements, including a high-performance AES
Advanced Encryption Standard
Advanced Encryption Standard is a specification for the encryption of electronic data. It has been adopted by the U.S. government and is now used worldwide. It supersedes DES...
encryption engine along with a notably small ball grid array
Ball grid array
A ball grid array is a type of surface-mount packaging used for integrated circuits.- Description :The BGA is descended from the pin grid array , which is a package with one face covered with pins in a grid pattern. These pins conduct electrical signals from the integrated circuit to the printed...
chip package the size of a US 1 cent coin
Cent (United States coin)
The United States one-cent coin, commonly known as a penny, is a unit of currency equaling one one-hundredth of a United States dollar. The cent's symbol is ¢. Its obverse has featured the profile of President Abraham Lincoln since 1909, the centennial of his birth. From 1959 to 2008, the reverse...
.
When this architecture was marketed it was often referred to as the "VIA C5".
Comparative die size
|- bgcolor="ccccff"! style="text-align: center; background: #ccccff;"|Processor
! style="text-align: center; background: #ccccff;"|Secondary
Cache (KiB)
! style="text-align: center; background: #ccccff;"|Die size
180 nm (mm²)
! style="text-align: center; background: #ccccff;"|Die size
150 nm (mm²)
! style="text-align: center; background: #ccccff;"|Die size
130 nm (mm²)
! style="text-align: center; background: #ccccff;"|Die size
90 nm (mm²)
|- align="center"
! C3 Samuel
| N/A || ? || N/A || N/A || N/A
|- align="center"
! C3 Samuel 2
| 64 || N/A || ? || N/A || N/A
|- align="center"
! C3 Ezra
| 64 || N/A || N/A || 52 || N/A
|- align="center"
! C3 Nehemiah
| 64 || N/A || N/A || 52 || N/A
|- align="center"
! C7 Esther
| 128 || N/A || N/A || N/A || 30
|- align="center"
! Athlon XP
| 256 || N/A || N/A || 84 || N/A
|- align="center"
! Athlon 64
| 512 || N/A || N/A || 144 || 84
|- align="center"
! Pentium M
| 2048 || N/A || N/A || N/A || 84
|- align="center"
! P4 Northwood
| 512 || N/A || N/A || 146 || N/A
|- align="center"
! P4 Prescott
| 1024 || N/A || N/A || N/A || 110
C7 Processor
The C7 Processor offers RoHS, carbon neutralCarbon neutral
Carbon neutrality, or having a net zero carbon footprint, refers to achieving net zero carbon emissions by balancing a measured amount of carbon released with an equivalent amount sequestered or offset, or buying enough carbon credits to make up the difference...
, and evolutionary architecture changes from the Nehemiah.
Design methodology
This has also enabled VIA to continue to scale the frequencies of their chips with each manufacturing process die shrink, while competitive products from Intel (such as the P4 Prescott) have encountered severe thermal management issues, although the new Intel Core
Intel Core
Yonah was the code name for Intel's first generation of 65 nm process mobile microprocessors, based on the Banias/Dothan-core Pentium M microarchitecture. SIMD performance has been improved through the addition of SSE3 instructions and improvements to SSE and SSE2 implementations, while integer...
generation of chips are substantially cooler.
To this extent, the performance gap that used to exist between VIA and competing x86 chips is still wide, but starting to narrow. Some of the design trade offs made by the VIA design team are worthy of study, as they run contrary to accepted wisdom.
C3
- Because memory performance is the limiting factor in many benchmarks, VIA processors implement large primary cacheCPU cacheA CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. The cache is a smaller, faster memory which stores copies of the data from the most frequently used main memory locations...
s, large TLBsTranslation Lookaside BufferA translation lookaside buffer is a CPU cache that memory management hardware uses to improve virtual address translation speed. All current desktop and server processors use a TLB to map virtual and physical address spaces, and it is ubiquitous in any hardware which utilizes virtual memory.The...
, and aggressive prefetchingPrefetchingPrefetching may refer to:* Instruction prefetch, in computer architecture, a microprocessor speedup technique* Prefetch input queue , in computer architecture, pre-loading machine code from memory...
, among other enhancements. While these features are not unique to VIA, memory access optimization is one area where they have not dropped features to save die space.
- Clock frequency is in general terms favored over increasing instructions per cycle. Complex features such as out-of-order instruction executionOut-of-order executionIn computer engineering, out-of-order execution is a paradigm used in most high-performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay...
are deliberately not implemented, because they impact the ability to increase the clock rate, require a lot of extra die space and power, and have little impact on performance in several common application scenarios.
- The pipeline is arranged to provide one-clock execution of the heavily used register–memory and memory–register forms of x86 instructions. Several frequently used instructions require fewer pipeline clocks than on other x86 processors.
- Infrequently used x86 instructions are implemented in microcodeMicrocodeMicrocode is a layer of hardware-level instructions and/or data structures involved in the implementation of higher level machine code instructions in many computers and other processors; it resides in special high-speed memory and translates machine instructions into sequences of detailed...
and emulated. This saves die space and reduces power consumption. The impact upon the majority of real world application scenarios is minimized.
- These design guidelines are derivative from the original RISC advocates, who stated a smaller set of instructions, better optimized, would deliver faster overall CPU performance. As it makes heavy use of memory operands, both as source and destination, the C3 design itself cannot qualify as RISC however.
Contracts
VIA’s embedded platform products have reportedly (2005) been adopted in Nissan’s car series, the LafestaNissan Lafesta
The Nissan Lafesta is a seven-seater minivan built by Nissan Motors for the Asian market. The name was derived from the Italian word festa, meaning holiday, festival or party, and according to the manufacturer "expresses a desire to spend an enjoyable time in the car together with family members or...
, Murano
Nissan Murano
The first generation Nissan Murano was powered by a 3.5 litre 245 bhp V6 engine, also used in several other Nissan models like the Altima, Maxima, and Nissan 350Z, but specifically tuned for use in the Murano. Available with standard front-wheel-drive and optional all-wheel-drive , the Nissan...
, and Presage
Nissan presage
The first generation Presage was launched by Nissan in June 1998 as a competitor to the Honda Odyssey and Toyota Estima. It was available with either seven or nine seats...
. These and other high volume industrial applications are starting to generate big profits for VIA as the small form factor and low power advantages close embedded deals.
Legal issues
On the basis of the IDT Centaur acquisition, VIA appears to have come into possession of at least three patents, which cover key aspects of processor technology used by Intel. On the basis of the negotiating leverage these patents offered, in 2003 VIA arrived at an agreement with Intel that allowed for a ten year patent cross license, enabling VIA to continue to design and manufacture x86 compatible CPUs. VIA was also granted a three year period of grace in which it could continue to use Intel socket infrastructure.See also
- List of VIA C3 microprocessors
- List of VIA Eden microprocessors
- List of VIA microprocessors
External links
- VIA-C3-Nehemiah review
- VIA C3 Gold CPU - 1 GHz
- VIA's Small & Quiet Eden Platform
- GHz_processor_review/ VIA C3 1 GHz Processor Review
- BlueSmoke - Review : VIA C3 Processor
- http://www.cpushack.net/VIA.html
- http://www.sandpile.org/impl/c5.htm
- http://www.sandpile.org/impl/c5xl.htm
- VIA C3 Kernel for FreeBSD