Verilog-A
Encyclopedia
Verilog-A is an industry standard modeling language for analog circuits. It is the continuous-time subset of Verilog-AMS
.
Verilog-A was created out of a need to standardize the Spectre
behavioral language in face of competition from VHDL (an IEEE standard), which was absorbing analog capability from other languages (e.g. MAST). Open Verilog International (OVI, the body that originally standardized Verilog) agreed to support the standardization, provided that it was part of a plan to create Verilog-AMS — a single language covering both analog and digital design. Verilog-A was an all-analog subset of Verilog-AMS that was the first phase of the project.
Unfortunately, there was considerable delay between the first Verilog-A language reference manual
and the full Verilog-AMS
, and in that time Verilog moved to the IEEE, leaving Verilog-AMS behind at Accellera
. Hence, the original goal of a single language standard is still to be achieved.
Verilog-AMS
Verilog-AMS is a derivative of the Verilog hardware description language. It includes analog and mixed-signal extensions in order to define the behavior of analog and mixed-signal systems. It extends the event-based simulator loops of Verilog/SystemVerilog/VHDL, by a continuous-time simulator,...
.
Verilog-A was created out of a need to standardize the Spectre
Spectre Circuit Simulator
Spectre is a SPICE-class circuit simulator. It provides the basic SPICE analyses and component models. It also supports the Verilog-A modeling language...
behavioral language in face of competition from VHDL (an IEEE standard), which was absorbing analog capability from other languages (e.g. MAST). Open Verilog International (OVI, the body that originally standardized Verilog) agreed to support the standardization, provided that it was part of a plan to create Verilog-AMS — a single language covering both analog and digital design. Verilog-A was an all-analog subset of Verilog-AMS that was the first phase of the project.
Unfortunately, there was considerable delay between the first Verilog-A language reference manual
Programming language reference
A programming language reference is an artifact that describes a programming language so that users and developers can understand the basic elements of and write computer programs in the target language....
and the full Verilog-AMS
Verilog-AMS
Verilog-AMS is a derivative of the Verilog hardware description language. It includes analog and mixed-signal extensions in order to define the behavior of analog and mixed-signal systems. It extends the event-based simulator loops of Verilog/SystemVerilog/VHDL, by a continuous-time simulator,...
, and in that time Verilog moved to the IEEE, leaving Verilog-AMS behind at Accellera
Accellera
Accellera is a standards organization that supports a mix of user and vendor standards and open interfaces development in the area of electronic design automation and IC design and manufacturing. It is less constrained than the IEEE and is therefore the starting place for many standards. Once...
. Hence, the original goal of a single language standard is still to be achieved.
External links
- Accellera Verilog Analog Mixed-Signal Group
- Language References Manuals
- The Designer's Guide to Verilog-AMS
- Verilog-AMS.com — Examples of models written in Verilog-A