In computing

Computing

Computing is usually defined as the activity of using and improving computer hardware and software. It is the computer-specific part of information technology...

, an Advanced Programmable Interrupt Controller (APIC) is a more complex Programmable Interrupt Controller

Programmable Interrupt Controller

In computing, a programmable interrupt controller is a device that is used to combine several sources of interrupt onto one or more CPU lines, while allowing priority levels to be assigned to its interrupt outputs. When the device has multiple interrupt outputs to assert, it will assert them in...

 (PIC) than Intel's original types such as the 8259A. APIC devices permit more complex priority models, and Advanced IRQ (Interrupt Request) management.

One of the best known APIC architectures, the Intel APIC Architecture

Intel APIC Architecture

The Intel APIC Architecture is a system of advanced programmable interrupt controllers designed by Intel for use in symmetric multiprocessor computer systems. It was originally implemented by the Intel 82093AA and 82489DX, and is found in most x86 SMP motherboards...

, has largely replaced the original 8259A PIC in newer x86 computers, starting with SMP systems when it replaced proprietary SMP solutions and on pretty much all PC compatibles since around late 2000 when Microsoft began encouraging PC vendors to enable it on uniprocessor systems and even made it a requirement of PC 2001 to enable it on desktop systems.
AMD and Cyrix once used the similar OpenPIC architecture; this can support up to 32 processors. After its failure however, AMD decided to license the Intel APIC Architecture

Intel APIC Architecture

The Intel APIC Architecture is a system of advanced programmable interrupt controllers designed by Intel for use in symmetric multiprocessor computer systems. It was originally implemented by the Intel 82093AA and 82489DX, and is found in most x86 SMP motherboards...

 for its AMD Athlon and later processors.

Controlling Device Requests

We know that I/O device interface generates an interrupt request when SIN or SOUT bit in its status register is =1.Interrupt requests are generated only by the I/O devices that some program is using.
Idle devices must not generate interrupt requests even if they are participating in I/O transfer operations. We need a way to enable or disable interrupts in order to control whether the device is generating an interrupt request.For this control we use Interrupt Enable bit in device's interface circuit.

Interrupt Enable (IE)

IE bit can be set or reset by processor.It can be a part of control or status register in which processor can write.Case1:When IE=1,interface circuit generates an interrupt request and sets its IRQ bit whenever its SIN or SOUT bit is set.Case2:When IE=0,interface circuit does not generate an interrupt request,regardless of the state of SIN or SOUT.
Interrupt enable bits IE(SIN) and IE(SOUT) are often used.IE(SIN) enables interrupts when SIN=1.IE(SOUT) enables interrupts when SOUT=1.

Summary

Interrupt requests can be controlled using two ways.I.At device end-An Interrupt Enable bit in a control register determines whether device is allowed to generate an interrupt request.II.At processor end-A priority structure and an interrupt mask in the PS determine whether a given interrupt request is accepted.

See also

• Intel 8259
  Intel 8259
  The Intel 8259 is a Programmable Interrupt Controller designed for the Intel 8085 and Intel 8086 microprocessors. The initial part was 8259, a later A suffix version was upward compatible and usable with the 8086 or 8088 processor...
  
  
• Programmable Interrupt Controller
  Programmable Interrupt Controller
  In computing, a programmable interrupt controller is a device that is used to combine several sources of interrupt onto one or more CPU lines, while allowing priority levels to be assigned to its interrupt outputs. When the device has multiple interrupt outputs to assert, it will assert them in...
  
   (PIC)
• Intel APIC Architecture
  Intel APIC Architecture
  The Intel APIC Architecture is a system of advanced programmable interrupt controllers designed by Intel for use in symmetric multiprocessor computer systems. It was originally implemented by the Intel 82093AA and 82489DX, and is found in most x86 SMP motherboards...
  
  
• Inter-processor interrupt
  Inter-Processor Interrupt
  An inter-processor interrupt is a special type of interrupt by which one processor may interrupt another processor in a multiprocessor system. IPIs are typically used to implement a cache coherency synchronization point.- Windows :...
  
   (IPI)
• Interrupt
  Interrupt
  In computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution....
  
  
• Interrupt handler
  Interrupt handler
  An interrupt handler, also known as an interrupt service routine , is a callback subroutine in microcontroller firmware, operating system or device driver whose execution is triggered by the reception of an interrupt...
  
  
• Interrupt latency
  Interrupt latency
  In real-time operating systems, interrupt latency is the time between the generation of an interrupt by a device and the servicing of the device which generated the interrupt. For many operating systems, devices are serviced as soon as the device's interrupt handler is executed...
  
  
• LAPIC
• Non-maskable interrupt
  Non-Maskable interrupt
  A non-maskable interrupt is a computer processor interrupt that cannot be ignored by standard interrupt masking techniques in the system. It is typically used to signal attention for non-recoverable hardware errors...
  
  (NMI)