An inter-processor interrupt (IPI) is a special type of interrupt

Interrupt

In computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution....

 by which one processor may interrupt another processor in a multiprocessor

Multiprocessor

Computer system having two or more processing units each sharing main memory and peripherals, in order to simultaneously process programs.Sometimes the term Multiprocessor is confused with the term Multiprocessing....

 system. IPIs are typically used to implement a cache coherency

Cache coherency

In computing, cache coherence refers to the consistency of data stored in local caches of a shared resource.When clients in a system maintain caches of a common memory resource, problems may arise with inconsistent data. This is particularly true of CPUs in a multiprocessing system...

 synchronization

Synchronization

Synchronization is timekeeping which requires the coordination of events to operate a system in unison. The familiar conductor of an orchestra serves to keep the orchestra in time....

 point.

Windows

In a Microsoft Windows

Microsoft Windows

Microsoft Windows is a series of operating systems produced by Microsoft.Microsoft introduced an operating environment named Windows on November 20, 1985 as an add-on to MS-DOS in response to the growing interest in graphical user interfaces . Microsoft Windows came to dominate the world's personal...

 based multiprocessor system, a processor may interrupt another processor for the following reasons:

1. Queue a DISPATCH_LEVEL interrupt to schedule a particular thread for execution.

2. Updating the processor's translation lookaside buffer

Translation Lookaside Buffer

A translation lookaside buffer is a CPU cache that memory management hardware uses to improve virtual address translation speed. All current desktop and server processors use a TLB to map virtual and physical address spaces, and it is ubiquitous in any hardware which utilizes virtual memory.The...

s cache.

3. System shutdown.

4. System crash.

5. Kernel debugger breakpoint.

IPIs are given an IRQL of 29.

Other uses

In x86

X86 architecture

The term x86 refers to a family of instruction set architectures based on the Intel 8086 CPU. The 8086 was launched in 1978 as a fully 16-bit extension of Intel's 8-bit based 8080 microprocessor and also introduced segmentation to overcome the 16-bit addressing barrier of such designs...

 based systems, an IPI synchronizes the cache and memory management unit

Memory management unit

A memory management unit , sometimes called paged memory management unit , is a computer hardware component responsible for handling accesses to memory requested by the CPU...

 (MMU) between processors.

See also

• Advanced Programmable Interrupt Controller
  Advanced Programmable Interrupt Controller
  In computing, an Advanced Programmable Interrupt Controller is a more complex Programmable Interrupt Controller than Intel's original types such as the 8259A...
  
   (APIC)
• Interrupt
  Interrupt
  In computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution....
  
  
• Interrupt handler
  Interrupt handler
  An interrupt handler, also known as an interrupt service routine , is a callback subroutine in microcontroller firmware, operating system or device driver whose execution is triggered by the reception of an interrupt...
  
  
• Non-maskable interrupt
  Non-Maskable interrupt
  A non-maskable interrupt is a computer processor interrupt that cannot be ignored by standard interrupt masking techniques in the system. It is typically used to signal attention for non-recoverable hardware errors...
  
   (NMI)
• Programmable Interrupt Controller
  Programmable Interrupt Controller
  In computing, a programmable interrupt controller is a device that is used to combine several sources of interrupt onto one or more CPU lines, while allowing priority levels to be assigned to its interrupt outputs. When the device has multiple interrupt outputs to assert, it will assert them in...
  
  (PIC)