Analog verification is a methodology for performing functional verification on analog, mixed-signal and RF integrated circuits and systems on chip

System-on-a-chip

A system on a chip or system on chip is an integrated circuit that integrates all components of a computer or other electronic system into a single chip. It may contain digital, analog, mixed-signal, and often radio-frequency functions—all on a single chip substrate...

. Discussion of analog verification began in 2005 when it started to become recognized that the analog portion of large mixed-signal chips had gotten so complex that a significant and ever increasing number of these chips were being designed with functional errors in the analog portion that prevented them from operating correctly.

Technical details

Analog verification is built on the idea that transistor level simulation will always be too slow to provide adequate functional verification. Instead, it is necessary to build simple and efficient models of the blocks that make up the analog portion of the design and use those to verify the design. Those models are typically written in Verilog

Verilog

In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...

 or Verilog-AMS

Verilog-AMS

Verilog-AMS is a derivative of the Verilog hardware description language. It includes analog and mixed-signal extensions in order to define the behavior of analog and mixed-signal systems. It extends the event-based simulator loops of Verilog/SystemVerilog/VHDL, by a continuous-time simulator,...

, but could also be written in VHDL or VHDL-AMS

VHDL-AMS

VHDL-AMS is a derivative of the hardware description language VHDL . It includes analog and mixed-signal extensions in order to define the behavior of analog and mixed-signal systems ....

. However, simply using a simple functional model is not sufficient. It is also necessary to build a comprehensive self-checking testbench, that thoroughly exercises the design and compare its response against a previously written specification for the design. Furthermore, this testbench should be applied in turn to both the model and the design. In this case, the design is represented with a transistor-level schematic. If both the model and the design pass all tests, and if the testbench is comprehensive, then this confirms that the model is consistent with the design and that the design is consistent with the specification.

Applying a comprehensive testbench to an entire analog functional unit such as an audio codec

Codec

A codec is a device or computer program capable of encoding or decoding a digital data stream or signal. The word codec is a portmanteau of "compressor-decompressor" or, more commonly, "coder-decoder"...

, power management unit, serdes

SerDes

A Serializer/Deserializer is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction...

, or RF transceiver, represented at the transistor level is impractical. So instead, the verification proceeds hierarchically. One first builds simple models and testbenches for individual blocks. The block-level testbenches are used to confirm that models match the implementation of the blocks and that the implementation matches the block-level specification. Then testbenches are built for the entire analog functional unit, and applied to the top-level schematic of that unit with the blocks represented with their now verified models. To further improve the tests, one can perform mixed-level simulation, where the testbench for the functional unit is applied with one or two blocks at the transistor level, and all others at the model level.