BRK
Encyclopedia
The 65xx family of microprocessor
s, consisting of the MOS Technology 6502
and its derivatives, the WDC 65C02
, WDC 65C802 and WDC 65C816
, all handle interrupt
s in a similar fashion. There are three hardware interrupt signals common to all 65xx processors and one software interrupt, the BRK instruction. The WDC 65C816 adds a fourth hardware interrupt—ABORT, useful for implementing virtual memory architectures—and the COP software interrupt instruction (also present in the 65C802), intended for use in a system with a coprocessor
of some type (e.g., a floating point processor).
The hardware interrupt signals are all active low, and are as follows:
The detection of a RESET signal causes the processor to enter a system initialization period of six clock cycles, after which it sets the interrupt disable flag in the status register
and loads the program counter
with the values stored at the processor initialization vector ($FFFC-$FFFD) before commencing execution.
The detection of an NMI or IRQ signal, as well as the execution of a BRK instruction, will cause the same overall sequence of events, which are, in order:
The behavior of the 65C816 when ABORT is asserted differs in some respects from the above description and is separately discussed below.
Note that the processor does not push the accumulator
and index register
s on to the stack—code in the interrupt handler must perform that task, as well as restore the registers at the termination of interrupt processing, as necessary. Also note that the vector for IRQ is the same as that for BRK in all eight bit 65xx processors, as well as in the 65C802/65C816 when operating in emulation mode. When operating in native mode, the 65C802/65C816 provide separate vectors for IRQ and BRK.
When set, the interrupt disable flag (the I bit in the status register) will disable detection of the IRQ signal, but will have no effect on any other interrupts. Additionally, with the 65(c)02 or the 65C816/65C802 operating in emulation mode, the copy of the status register that is pushed on to the stack will have the B flag set if a BRK was the cause of the interrupt, or cleared if an IRQ was the cause. Hence the interrupt service routine must retrieve a copy of the saved status register from where it was pushed onto the stack and check the status of the B flag in order to distinguish between an IRQ and a BRK. This requirement is eliminated when operating the 65C802/65C816 in native mode, due to the separate vectors for the two interrupt types.
or a memory access violation. Hence the response to an ABORT interrupt is different in behavior than that of IRQ and/or NMI when asserted. Also, achieving correct operation in response to ABORT requires that the interrupt occur at the proper time during the machine cycle, whereas no such requirement exists for IRQ or NMI.
When ABORT is asserted during a valid memory cycle (that is, when the processor has asserted the VDA and/or VPA status outputs), the following sequence of events will occur:
As the address pushed to the stack is that of the aborted instruction rather than the contents of the program counter, executing an RTI following an ABORT interrupt will cause the processor to return to the aborted instruction, rather than the next instruction, as would be the case with the other interrupts.
In order for the processor to correctly respond to ABORT, system logic must assert the interrupt as soon as a valid address has been placed on the bus and it has been determined that the address constitutes a page fault or a memory access violation. Hence the logic must not assert ABORT until the processor has asserted the VDA or VPA signals. Also, ABORT must remain asserted until the fall of the phase-two clock and then be immediately released. If these timing constraints are not observed, the ABORT interrupt handler itself may be aborted, causing registers and/or memory to be changed in a possibly-undefined manner.
6502, the simultaneous assertion of a hardware interrupt line and execution of BRK was not accounted for in the design—the BRK instruction will be ignored in such a case. Also, the status of the decimal mode
flag in the processor status register is unchanged following an interrupt of any kind. This behaviour can potentially result in a difficult to locate bug
in the interrupt handler
if decimal mode happens to be enabled at the time of an interrupt. These anomalies were corrected in all CMOS
versions of the processor.
A historical use of BRK has been to assist in patching PROMs
when bugs were discovered in a system's firmware
. A typical technique often used during firmware development was to arrange for the BRK vector to point to an unprogrammed "patch area" in the PROM. In the event a bug was discovered, patching would be accomplished by "blowing" all of the fuses at the address where the faulty instruction was located, thus changing the instruction's opcode
to $00. Upon executing the resulting BRK, the MPU would be redirected to the patch area, into which suitable patch code would be written. Often, the patch area code started by "sniffing the stack" to determine the address at which the bug was encountered, potentially allowing for the presence of more than one patch in the PROM. The use of BRK for PROM patching diminished once EPROM
s and EEPROM
s became commonly available.
Another use of BRK in software development is as a debugging aid in conjunction with a machine language monitor. By overwriting an opcode with BRK ($00) and directing the BRK hardware vector to the entry point of the monitor, one can cause a program to halt at any desired point, allowing the monitor to take control. At that time, one may examine memory, view the processor's register values, patch code, etc. Debugging, as advocated by Kuckes and Thompson, can be facilitated by liberally sprinkling one's code with NOP
instructions (opcode EA) that can be replaced by BRK instructions without altering the actual behaviour of the program being debugged.
A characteristic of the BRK and COP instructions is that the processor treats either as a two byte instruction: the opcode itself and the following byte, which is referred to as the "signature." Upon execution of BRK or COP, the processor will add two to the program counter prior to pushing it to the stack. Hence when RTI (ReTurn from Interrupt) is executed, the interrupted program will continue at the address immediately following the signature. If BRK is used as a debugging device, the program counter may have to be adjusted to point to the signature in order for execution to resume where expected. Alternatively, a NOP may be inserted as a signature "placeholder," in which case no program counter adjustment will be required.
The fact that BRK and COP double-increment the program counter before pushing it to the stack facilitates the technique of treating them as supervisor call instruction
s, as found on some mainframe computer
s. The usual procedure is to treat the signature as an operating system service index. The operating system BRK or COP handler would retrieve the value of the program counter pushed to the stack, decrement it and read from the resulting memory location to get the signature. After converting the signature to a zero-based index, a simple lookup table
can be consulted to load the program counter with the address of the proper service routine. Upon completion of the service routine, the RTI instruction would be used to return control to the program that made the operating system call. Note that the signature for BRK may be any value, whereas the signature for COP should be limited to the range $00-$7F.
The use of BRK and/or COP to request an operating system service means user applications do not have to know the entry address of each operating system function, only the correct signature byte to invoke the desired operation. Hence relocation of the operating system in memory will not break compatibility with existing user applications. Also, as executing BRK or COP always vectors the processor to the same address, simple code may be used to preserve the registers on the stack prior to turning control over to the requested service. However, this programming model will result in somewhat slower execution as compared to calling a service as a subroutine
. Also, interrupt requests will have been disabled by executing BRK or COP. requiring that the operating system re-enable them.
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
s, consisting of the MOS Technology 6502
MOS Technology 6502
The MOS Technology 6502 is an 8-bit microprocessor that was designed by Chuck Peddle and Bill Mensch for MOS Technology in 1975. When it was introduced, it was the least expensive full-featured microprocessor on the market by a considerable margin, costing less than one-sixth the price of...
and its derivatives, the WDC 65C02
WDC 65C02
The Western Design Center WDC 65C02 microprocessor is an upgraded CMOS version of the popular NMOS-based MOS Technology 6502 8-bit CPU — the CMOS redesign being made by Bill Mensch of the Western Design Center...
, WDC 65C802 and WDC 65C816
WDC 65816/65802
The W65C816S is a 16-bit microprocessor developed by the Western Design Center . The W65C816S is an enhanced version of the WDC 65C02 8-bit MPU, itself a CMOS enhancement of the venerable MOS Technology 6502 NMOS MPU...
, all handle interrupt
Interrupt
In computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution....
s in a similar fashion. There are three hardware interrupt signals common to all 65xx processors and one software interrupt, the BRK instruction. The WDC 65C816 adds a fourth hardware interrupt—ABORT, useful for implementing virtual memory architectures—and the COP software interrupt instruction (also present in the 65C802), intended for use in a system with a coprocessor
Coprocessor
A coprocessor is a computer processor used to supplement the functions of the primary processor . Operations performed by the coprocessor may be floating point arithmetic, graphics, signal processing, string processing, or encryption. By offloading processor-intensive tasks from the main processor,...
of some type (e.g., a floating point processor).
Interrupt types
| Interrupt | Vector (hexadecimal) | |
|---|---|---|
| LSB | MSB | |
| ABORT | FFF8 | FFF9 |
| COP | FFF4 | FFF5 |
| NMI | FFFA | FFFB |
| RESET | FFFC | FFFD |
| IRQ/BRK | FFFE | FFFF |
The hardware interrupt signals are all active low, and are as follows:
-
- RESET:a reset signalReset (Computing)In a computer or data transmission system, to reset means to clear any pending errors or events and bring a system to normal condition or initial state usually in a controlled manner. It is usually done in response to an error condition when it is impossible or undesirable for a processing activity...
, level-triggered - NMI:a non-maskable interrupt, edge-triggered
- IRQ:a maskable interrupt, level-triggered
- ABORT:a special-purpose, non-maskable interrupt (65C816 only, see below), level-triggered
- RESET:a reset signal
The detection of a RESET signal causes the processor to enter a system initialization period of six clock cycles, after which it sets the interrupt disable flag in the status register
Status register
A status register or flag register is a collection of flag bits for a processor. An example is the FLAGS register of the x86 architecture....
and loads the program counter
Program counter
The program counter , commonly called the instruction pointer in Intel x86 microprocessors, and sometimes called the instruction address register, or just part of the instruction sequencer in some computers, is a processor register that indicates where the computer is in its instruction sequence...
with the values stored at the processor initialization vector ($FFFC-$FFFD) before commencing execution.
| Interrupt | Vector (hexadecimal) | |
|---|---|---|
| LSB | MSB | |
| ABORT | 00FFE8 | 00FFE9 |
| COP | 00FFE4 | 00FFE5 |
| BRK | 00FFE6 | 00FFE7 |
| NMI | 00FFEA | 00FFEB |
| RESET | None | |
| IRQ | 00FFEE | 00FFEF |
The detection of an NMI or IRQ signal, as well as the execution of a BRK instruction, will cause the same overall sequence of events, which are, in order:
- The processor completes the current instruction and updates registers or memory as required before responding to the interrupt.
- The program bank register (PBR, the A16-A23 part of the address bus) is pushed onto the stackStack (data structure)In computer science, a stack is a last in, first out abstract data type and linear data structure. A stack can have any abstract data type as an element, but is characterized by only three fundamental operations: push, pop and stack top. The push operation adds a new item to the top of the stack,...
(65C816/65C802 only when operating in native mode). - The most significant byte (MSB) of the program counter is pushed onto the stack.
- The least significant byte (LSB) of the program counter is pushed onto the stack.
- The status register is pushed onto the stack.
- The interrupt disable flag is set in the status register.
- PBR is loaded with $00 (65C816/65C802 only when operating in native mode).
- The program counter is loaded from the relevant vector (see tables).
The behavior of the 65C816 when ABORT is asserted differs in some respects from the above description and is separately discussed below.
Note that the processor does not push the accumulator
Accumulator (computing)
In a computer's central processing unit , an accumulator is a register in which intermediate arithmetic and logic results are stored. Without a register like an accumulator, it would be necessary to write the result of each calculation to main memory, perhaps only to be read right back again for...
and index register
Index register
An index registerCommonly known as a B-line in early British computers. in a computer's CPU is a processor register used for modifying operand addresses during the run of a program, typically for doing vector/array operations...
s on to the stack—code in the interrupt handler must perform that task, as well as restore the registers at the termination of interrupt processing, as necessary. Also note that the vector for IRQ is the same as that for BRK in all eight bit 65xx processors, as well as in the 65C802/65C816 when operating in emulation mode. When operating in native mode, the 65C802/65C816 provide separate vectors for IRQ and BRK.
When set, the interrupt disable flag (the I bit in the status register) will disable detection of the IRQ signal, but will have no effect on any other interrupts. Additionally, with the 65(c)02 or the 65C816/65C802 operating in emulation mode, the copy of the status register that is pushed on to the stack will have the B flag set if a BRK was the cause of the interrupt, or cleared if an IRQ was the cause. Hence the interrupt service routine must retrieve a copy of the saved status register from where it was pushed onto the stack and check the status of the B flag in order to distinguish between an IRQ and a BRK. This requirement is eliminated when operating the 65C802/65C816 in native mode, due to the separate vectors for the two interrupt types.
ABORT interrupt
The 65C816's ABORT input is intended to provide the means to interrupt the processor when a hardware exception is detected, such as a page faultPage fault
A page fault is a trap to the software raised by the hardware when a program accesses a page that is mapped in the virtual address space, but not loaded in physical memory. In the typical case the operating system tries to handle the page fault by making the required page accessible at a location...
or a memory access violation. Hence the response to an ABORT interrupt is different in behavior than that of IRQ and/or NMI when asserted. Also, achieving correct operation in response to ABORT requires that the interrupt occur at the proper time during the machine cycle, whereas no such requirement exists for IRQ or NMI.
When ABORT is asserted during a valid memory cycle (that is, when the processor has asserted the VDA and/or VPA status outputs), the following sequence of events will occur:
- The processor completes the current instruction but does not change the registers or memory in any way—the results of the completed instruction are discarded.
- PBR is pushed onto the stack.
- The most significant byte (MSB) of the aborted instruction's address is pushed onto the stack.
- The least significant byte (LSB) of the aborted instruction's address is pushed onto the stack.
- The status register is pushed onto the stack.
- The interrupt disable flag is set in the status register.
- PBR is loaded with $00.
- The program counter is loaded from the ABORT vector (see tables).
As the address pushed to the stack is that of the aborted instruction rather than the contents of the program counter, executing an RTI following an ABORT interrupt will cause the processor to return to the aborted instruction, rather than the next instruction, as would be the case with the other interrupts.
In order for the processor to correctly respond to ABORT, system logic must assert the interrupt as soon as a valid address has been placed on the bus and it has been determined that the address constitutes a page fault or a memory access violation. Hence the logic must not assert ABORT until the processor has asserted the VDA or VPA signals. Also, ABORT must remain asserted until the fall of the phase-two clock and then be immediately released. If these timing constraints are not observed, the ABORT interrupt handler itself may be aborted, causing registers and/or memory to be changed in a possibly-undefined manner.
Interrupt anomalies
In the NMOSNMOS logic
N-type metal-oxide-semiconductor logic uses n-type metal-oxide-semiconductor field effect transistors to implement logic gates and other digital circuits...
6502, the simultaneous assertion of a hardware interrupt line and execution of BRK was not accounted for in the design—the BRK instruction will be ignored in such a case. Also, the status of the decimal mode
Binary-coded decimal
In computing and electronic systems, binary-coded decimal is a digital encoding method for numbers using decimal notation, with each decimal digit represented by its own binary sequence. In BCD, a numeral is usually represented by four bits which, in general, represent the decimal range 0 through 9...
flag in the processor status register is unchanged following an interrupt of any kind. This behaviour can potentially result in a difficult to locate bug
Software bug
A software bug is the common term used to describe an error, flaw, mistake, failure, or fault in a computer program or system that produces an incorrect or unexpected result, or causes it to behave in unintended ways. Most bugs arise from mistakes and errors made by people in either a program's...
in the interrupt handler
Interrupt handler
An interrupt handler, also known as an interrupt service routine , is a callback subroutine in microcontroller firmware, operating system or device driver whose execution is triggered by the reception of an interrupt...
if decimal mode happens to be enabled at the time of an interrupt. These anomalies were corrected in all CMOS
CMOS
Complementary metal–oxide–semiconductor is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits...
versions of the processor.
Using BRK and COP
As previously noted, BRK and COP are software interrupts and, as such, may be used in a variety of ways to implement system functions.A historical use of BRK has been to assist in patching PROMs
Programmable read-only memory
A programmable read-only memory or field programmable read-only memory or one-time programmable non-volatile memory is a form of digital memory where the setting of each bit is locked by a fuse or antifuse. Such PROMs are used to store programs permanently...
when bugs were discovered in a system's firmware
Firmware
In electronic systems and computing, firmware is a term often used to denote the fixed, usually rather small, programs and/or data structures that internally control various electronic devices...
. A typical technique often used during firmware development was to arrange for the BRK vector to point to an unprogrammed "patch area" in the PROM. In the event a bug was discovered, patching would be accomplished by "blowing" all of the fuses at the address where the faulty instruction was located, thus changing the instruction's opcode
Opcode
In computer science engineering, an opcode is the portion of a machine language instruction that specifies the operation to be performed. Their specification and format are laid out in the instruction set architecture of the processor in question...
to $00. Upon executing the resulting BRK, the MPU would be redirected to the patch area, into which suitable patch code would be written. Often, the patch area code started by "sniffing the stack" to determine the address at which the bug was encountered, potentially allowing for the presence of more than one patch in the PROM. The use of BRK for PROM patching diminished once EPROM
EPROM
An EPROM , or erasable programmable read only memory, is a type of memory chip that retains its data when its power supply is switched off. In other words, it is non-volatile. It is an array of floating-gate transistors individually programmed by an electronic device that supplies higher voltages...
s and EEPROM
EEPROM
EEPROM stands for Electrically Erasable Programmable Read-Only Memory and is a type of non-volatile memory used in computers and other electronic devices to store small amounts of data that must be saved when power is removed, e.g., calibration...
s became commonly available.
Another use of BRK in software development is as a debugging aid in conjunction with a machine language monitor. By overwriting an opcode with BRK ($00) and directing the BRK hardware vector to the entry point of the monitor, one can cause a program to halt at any desired point, allowing the monitor to take control. At that time, one may examine memory, view the processor's register values, patch code, etc. Debugging, as advocated by Kuckes and Thompson, can be facilitated by liberally sprinkling one's code with NOP
NOP
In computer science, NOP or NOOP is an assembly language instruction, sequence of programming language statements, or computer protocol command that effectively does nothing at all....
instructions (opcode EA) that can be replaced by BRK instructions without altering the actual behaviour of the program being debugged.
A characteristic of the BRK and COP instructions is that the processor treats either as a two byte instruction: the opcode itself and the following byte, which is referred to as the "signature." Upon execution of BRK or COP, the processor will add two to the program counter prior to pushing it to the stack. Hence when RTI (ReTurn from Interrupt) is executed, the interrupted program will continue at the address immediately following the signature. If BRK is used as a debugging device, the program counter may have to be adjusted to point to the signature in order for execution to resume where expected. Alternatively, a NOP may be inserted as a signature "placeholder," in which case no program counter adjustment will be required.
The fact that BRK and COP double-increment the program counter before pushing it to the stack facilitates the technique of treating them as supervisor call instruction
Supervisor call instruction
In the System/360 line of IBM mainframe computers up to contemporary zSeries, a Supervisor Call instruction is an instruction used to cause an interrupt in order to perform a Supervisor Call, which is distinct and separate from a system call, usually termed a Program Call .IBM mainframes in the...
s, as found on some mainframe computer
Mainframe computer
Mainframes are powerful computers used primarily by corporate and governmental organizations for critical applications, bulk data processing such as census, industry and consumer statistics, enterprise resource planning, and financial transaction processing.The term originally referred to the...
s. The usual procedure is to treat the signature as an operating system service index. The operating system BRK or COP handler would retrieve the value of the program counter pushed to the stack, decrement it and read from the resulting memory location to get the signature. After converting the signature to a zero-based index, a simple lookup table
Lookup table
In computer science, a lookup table is a data structure, usually an array or associative array, often used to replace a runtime computation with a simpler array indexing operation. The savings in terms of processing time can be significant, since retrieving a value from memory is often faster than...
can be consulted to load the program counter with the address of the proper service routine. Upon completion of the service routine, the RTI instruction would be used to return control to the program that made the operating system call. Note that the signature for BRK may be any value, whereas the signature for COP should be limited to the range $00-$7F.
The use of BRK and/or COP to request an operating system service means user applications do not have to know the entry address of each operating system function, only the correct signature byte to invoke the desired operation. Hence relocation of the operating system in memory will not break compatibility with existing user applications. Also, as executing BRK or COP always vectors the processor to the same address, simple code may be used to preserve the registers on the stack prior to turning control over to the requested service. However, this programming model will result in somewhat slower execution as compared to calling a service as a subroutine
Subroutine
In computer science, a subroutine is a portion of code within a larger program that performs a specific task and is relatively independent of the remaining code....
. Also, interrupt requests will have been disabled by executing BRK or COP. requiring that the operating system re-enable them.