Common Power Format
Encyclopedia
The Si2 Common Power Format, or CPF is a file format
for specifying power-saving techniques early in the design process. In the design of integrated circuit
s, saving power is a primary goal, and designers are forced to use sophisticated techniques such as clock gating
, multi-voltage logic, and turning off the power entirely to inactive blocks. These techniques require a consistent implementation in the design steps of logic design, implementation, and verification. For example, if multiple different power supplies are used, then logic synthesis
must insert level shifters, place
and route
must deal with them correctly, and other tools such as static timing analysis
and formal verification
must understand these components. As power became an increasingly pressing concern, each tool independently added the features needed. Although this made it possible to build low power flows, it was difficult and error prone since the same information needed to be specified several times, in several formats, to many different tools. CPF was created as a common format that many tools can use to specify power-specific data, so that power intent only need be entered once and can be used consistently by all tools. The aim of CPF is to support an automated, power-aware design infrastructure.
Associated with CPF is the Power Forward Initiative (PFI), a group of companies that collaborate to drive low-power design methodology and have contributed to the development of the CPF v1.0 specification. PFI membership spans EDA
, IP, library, foundry fables, ASIC, IDM, and equipment companies. In March 2007, CPF v1.0 was contributed to the Silicon Integration Initiative
(Si2) where it was ratified by Si2’s Low Power Coalition (LPC) as a Si2 standard. The LPC controls the ongoing evolution of the CPF v1.0 standard.
Power control logic
Definition and verification of power modes (standby, sleep, etc.)
designed the early versions of CPF, then contributed it to Si2. This was followed shortly by an alternative effort, the Unified Power Format
or UPF, proposed as an IEEE standard as opposed to an Si2 standard. UPF has been driven mainly by Synopsys
, Mentor Graphics
and Magma
. The technical differences between the two formats are relatively minor, but the political considerations are harder to overcome. Not surprisingly, the Cadence Low-Power Solution supports Si2’s CPF, whereas the Synopsys, and Mentor Graphics offerings all support UPF. Magma supports both CPF and UPF.
An attempt at convergence is taking place in the Low Power Coalition at Si2, see this link for details: http://www.si2.org/?page=984
File format
A file format is a particular way that information is encoded for storage in a computer file.Since a disk drive, or indeed any computer storage, can store only bits, the computer must have some way of converting information to 0s and 1s and vice-versa. There are different kinds of formats for...
for specifying power-saving techniques early in the design process. In the design of integrated circuit
Integrated circuit
An integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...
s, saving power is a primary goal, and designers are forced to use sophisticated techniques such as clock gating
Clock gating
Clock gating is a power-saving technique used in many synchronous circuits-Description:Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding more logic to a circuit to prune the clock tree...
, multi-voltage logic, and turning off the power entirely to inactive blocks. These techniques require a consistent implementation in the design steps of logic design, implementation, and verification. For example, if multiple different power supplies are used, then logic synthesis
Logic synthesis
In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level , is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog...
must insert level shifters, place
Placement (EDA)
Placement is an essential step in electronic design automation - the portion of the physical design flow that assigns exact locations for various circuitcomponents within the chip’s core area...
and route
Routing (EDA)
In electronic design, wire routing, commonly called simply routing, is a step in the design of printed circuit boards and integrated circuits . It builds on a preceding step, called placement, which determines the location of each active element of an IC or component on a PCB...
must deal with them correctly, and other tools such as static timing analysis
Static timing analysis
Static Timing Analysis is a method of computing the expected timing of a digital circuit without requiring simulation.High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate...
and formal verification
Formal verification
In the context of hardware and software systems, formal verification is the act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal methods of mathematics .- Usage :Formal verification can be...
must understand these components. As power became an increasingly pressing concern, each tool independently added the features needed. Although this made it possible to build low power flows, it was difficult and error prone since the same information needed to be specified several times, in several formats, to many different tools. CPF was created as a common format that many tools can use to specify power-specific data, so that power intent only need be entered once and can be used consistently by all tools. The aim of CPF is to support an automated, power-aware design infrastructure.
Associated with CPF is the Power Forward Initiative (PFI), a group of companies that collaborate to drive low-power design methodology and have contributed to the development of the CPF v1.0 specification. PFI membership spans EDA
Electronic design automation
Electronic design automation is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits...
, IP, library, foundry fables, ASIC, IDM, and equipment companies. In March 2007, CPF v1.0 was contributed to the Silicon Integration Initiative
Silicon Integration Initiative
Silicon Integration Initiative is a non-profit consortium of industry-leading semiconductor, systems, EDA, and manufacturing companies, focused on improving the way integrated circuits are designed and manufactured in order to speed time to market, reduce costs, and meet the challenges of...
(Si2) where it was ratified by Si2’s Low Power Coalition (LPC) as a Si2 standard. The LPC controls the ongoing evolution of the CPF v1.0 standard.
Contents
Constructs expressing power domains and their power supplies:- Logical design: hierarchical modules can be specified as belonging to specific power supply domains
- Physical design: explicit power/ground nets and connectivity can be specified per cell or block.
- Analysis: different timing library data for cases where the same cell is used in different power domains
Power control logic
- Specification of level shifter logic - special cells needed when signals traverse between blocks of different supply voltage.
- Specification of isolation logic - what special logic is needed for signals that traverse between blocks that can be powered up and down independently.
- Specification of state-retention logic - when blocks are switched off entirely, how is the state retained?
- Specification of switch logic and control signals - how are blocks switched on and off?
Definition and verification of power modes (standby, sleep, etc.)
- Mode definitions
- Mode transition expressions
History and controversy
Cadence Design SystemsCadence Design Systems
Cadence Design Systems, Inc is an electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc...
designed the early versions of CPF, then contributed it to Si2. This was followed shortly by an alternative effort, the Unified Power Format
Unified Power Format
Unified Power Format is the popular name of the Institute of Electrical and Electronics Engineers standard for specifying power intent in power optimization of electronic design automation...
or UPF, proposed as an IEEE standard as opposed to an Si2 standard. UPF has been driven mainly by Synopsys
Synopsys
Synopsys, Inc. is one of the largest companies in the Electronic Design Automation industry. Synopsys' first and best-known product is Design Compiler, a logic-synthesis tool. Synopsys offers a wide range of other products used in the design of an application-specific integrated circuit...
, Mentor Graphics
Mentor Graphics
Mentor Graphics, Inc is a US-based multinational corporation dealing in electronic design automation for electrical engineering and electronics, as of 2004, ranked third in the EDA industry it helped create...
and Magma
Magma Design Automation
Magma Design Automation is a software company in the electronic design automation industry. The company was founded in 1997 and maintains headquarters in San Jose, California, with facilities throughout North America, Europe, Japan, Asia and India....
. The technical differences between the two formats are relatively minor, but the political considerations are harder to overcome. Not surprisingly, the Cadence Low-Power Solution supports Si2’s CPF, whereas the Synopsys, and Mentor Graphics offerings all support UPF. Magma supports both CPF and UPF.
An attempt at convergence is taking place in the Low Power Coalition at Si2, see this link for details: http://www.si2.org/?page=984