Placement (EDA) - AbsoluteAstronomy.com

Placement is an essential step in electronic design automation

Electronic design automation

Electronic design automation is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits...

- the portion of the physical design flow that assigns exact locations for various circuit
components within the chip’s core area. An inferior placement assignment will not only affect the
chip

Integrated circuit

An integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...

's performance but might also make it nonmanufacturable by producing excessive wirelength, which
is beyond available routing

Routing (EDA)

In electronic design, wire routing, commonly called simply routing, is a step in the design of printed circuit boards and integrated circuits . It builds on a preceding step, called placement, which determines the location of each active element of an IC or component on a PCB...

resources. Consequently, a placer must perform the assignment while optimizing
a number of objectives to ensure that a circuit meets its performance demands. Typical placement
objectives include

Total wirelength: Minimizing the total wirelength, or the sum of the length of all the wires in the design, is the primary objective of most existing placers. This not only helps minimize chip size, and hence cost, but also minimizes power and delay, which are proportional to the wirelength (This assumes long wires have additional buffering inserted; all modern design flows do this.)
Timing: The clock
Clock signal
In electronics and especially synchronous digital circuits, a clock signal is a particular type of signal that oscillates between a high and a low state and is utilized like a metronome to coordinate actions of circuits...

cycle of a chip is determined by the delay of its longest path, usually referred to as the critical path. Given a performance specification, a placer must ensure that no path exists with delay exceeding the maximum specified delay.
Congestion: While it is necessary to minimize the total wirelength to meet the total routing resources, it is also necessary to meet the routing resources within various local regions of the chip’s core area. A congested region might lead to excessive routing detours, or make it impossible to complete all routes.
Power: Power minimization typically involves distributing the locations of cell components so as to reduce the overall power consumption, alleviate hot spots, and smooth temperature gradients.
A secondary objective is placement runtime minimization.

Placement within the EDA design flow

A placer takes a given synthesized
circuit netlist

Netlist

The word netlist can be used in several different contexts, but perhaps the most popular is in the field of electronic design. In this context, a "netlist" describes the connectivity of an electronic design....

together with a technology library and produces a valid placement layout. The layout
is optimized according to the aforementioned objectives and ready for cell resizing and buffering — a step
essential for timing

Static timing analysis

Static Timing Analysis is a method of computing the expected timing of a digital circuit without requiring simulation.High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate...

and signal integrity

Signal integrity

Signal integrity or SI is a set of measures of the quality of an electrical signal. In digital electronics, a stream of binary values is represented by a voltage waveform. However, digital signals are fundamentally analog in nature, and all signals are subject to effects such as noise,...

satisfaction.
Clock-tree

Clock Distribution Networks

In a synchronous digital system,the clock signal is used to define a timereference for the movement of data within that system. The clock distribution network distributes the clock signal from a common point to all the elements that need it.Since this function isvital to the operation of a...

synthesis and routing

Routing (EDA)

follow, completing the physical design process.
In many cases, parts of, or the entire, physical design flow are iterated a number
of times until design closure

Design closure

Design closure is the process by which a VLSI design is modified from its initial description to meet a growing list of design constraints and objectives....

is achieved.

In the case of application-specific integrated circuit

Application-specific integrated circuit

An application-specific integrated circuit is an integrated circuit customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC...

s, or ASICs, the chip’s core layout area comprises a
number of fixed height rows, with either some or no space between them. Each row consists of a number
of sites which can be occupied by the circuit components. A free site is a site that is not occupied by any component. Circuit components are either standard cells, macro blocks, or I/O pads. Standard cells have a
fixed height equal to a row’s height, but have variable widths. The width of a cell is an integral number of
sites. On the other hand, blocks are typically larger than cells and have variable heights that can stretch a
multiple number of rows. Some blocks can have preassigned
locations — say from a previous floorplanning process — which limit the placer’s task to assigning locations
for just the cells. In this case, the blocks are typically referred to by fixed blocks. Alternatively, some or
all of the blocks may not have preassigned locations. In this case, they have to be placed with the cells in
what is commonly referred to as mixed-mode placement.

In addition to ASICs, placement retains its prime importance in gate array structures such as field-programmable gate array

Field-programmable gate array

A field-programmable gate array is an integrated circuit designed to be configured by the customer or designer after manufacturing—hence "field-programmable"...

s (FPGAs). In FPGAs, placement maps the circuit’s subcircuits into programmable FPGA logic blocks in a manner that guarantees the completion of the subsequent stage of routing.

Basic techniques

Analytical techniques approximate the wirelength objective using quadratic or nonlinear formulations.
The advent of min-cut partitioners paved the way to the introduction of min-cut placers.
Another thread of placement techniques started with the proposal of simulated annealing
Simulated annealing
Simulated annealing is a generic probabilistic metaheuristic for the global optimization problem of locating a good approximation to the global optimum of a given function in a large search space. It is often used when the search space is discrete...

as a general combinatorial optimization technique.

Placement within the EDA design flow

Basic techniques

See also

Further reading/External links