Design closure
Encyclopedia
Design closure is the process by which a VLSI
design is modified from its initial description to meet a growing list of design constraints and objectives.
Every step in the IC design (such as static timing analysis
, placement
, routing
, and so on) is already complex and often forms its own field of study. This article, however, looks at the overall design closure process, which takes a chip from its initial design state to the final form in which all of its design constraints are met.
(or less) is better. For example, yield is generally an objective, which is maximized to lower manufacturing cost. For the purposes of design closure, the distinction between constraints and objectives is not important; this article uses the words interchangeably.
Modern design closure has grown orders of magnitude more complex. Modern logic chips can have tens to hundreds of millions of logic elements switching at speeds of several
GHz. This improvement has been driven by Moore’s law of scaling of technology, and has introduced many new design considerations. As a result, a modern VLSI designer must consider the performance of a chip against a list of dozens of design constraints and objectives including performance, power, signal integrity
, reliability, and yield. In response to this growing list of constraints, the design closure flow has evolved from a simple linear list of tasks to a very complex, highly iterative flow such as the following simplified ASIC design flow:
A good example of this evolution can be found in the signal integrity
constraint. In the mid-1990s (180 nm
node), industry visionaries were describing the impending dangers of coupling noise long before chips were
failing. By the mid-late 1990s, noise problems were cropping up in advanced microprocessor designs.
By 2000, automated noise analysis tools were available and were used to guide manual fix-up. The total
number of noise problems identified by the analysis tools identified by the flow quickly became too many
to correct manually. In response, CAD companies developed the noise avoidance flows that are currently in
use in the industry.
At any point in time, the constraints in the design flow are at different stages of their life cycle. At the
time of this writing, for example, performance optimization is the most mature and is well into the fifth
phase with the widespread use of timing-driven design flows. Power- and defect-oriented yield optimization
is well into the fourth phase; power supply integrity, a type of noise constraint, is in the third phase;
circuit-limited yield optimization is in the second phase, etc. A list of the first-phase impending constraint
crises can always be found in the International Technology Roadmap for Semiconductors
(ITRS) 15-year-outlook technology roadmaps.
As a constraint matures in the design flow, it tends to work its way from the end of the flow to the beginning.
As it does this, it also tends to increase in complexity and in the degree that it contends with other constraints.
Constraints tend to move up in the flow due to one of the basic paradoxes of design: accuracy vs.
influence. Specifically, the earlier in a design flow a constraint is addressed, the more flexibility there is to
address the constraint. Ironically, the earlier one is in a design flow, the more difficult it is to predict compliance.
For example, an architectural decision to pipeline a logic function can have a far greater impact on
total chip performance than any amount of postrouting fix-up. At the same time, accurately predicting the
performance impact of such a change before the chip logic is synthesized, let alone placed or routed, is very
difficult. This paradox has shaped the evolution of the design closure flow in several ways. First, it requires
that the design flow is no longer composed of a linear set of discrete steps. In the early stages of VLSI it was
sufficient to break the design into discrete stages, i.e., first do logic synthesis, then do placement, then do
routing. As the number and complexity of design closure constraints has increased, the linear design flow
has broken down. In the past if there were too many timing constraint violations left after routing, it was
necessary to loop back, modify the tool settings slightly, and reexecute the previous placement steps. If the
constraints were still not met, it was necessary to reach further back in the flow and modify the chip logic
and repeat the synthesis and placement steps. This type of looping is both time consuming and unable to
guarantee convergence i.e., it is possible to loop back in the flow to correct one constraint violation only to
find that the correction induced another unrelated violation.
Integrated circuit
An integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...
design is modified from its initial description to meet a growing list of design constraints and objectives.
Every step in the IC design (such as static timing analysis
Static timing analysis
Static Timing Analysis is a method of computing the expected timing of a digital circuit without requiring simulation.High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate...
, placement
Placement (EDA)
Placement is an essential step in electronic design automation - the portion of the physical design flow that assigns exact locations for various circuitcomponents within the chip’s core area...
, routing
Routing (EDA)
In electronic design, wire routing, commonly called simply routing, is a step in the design of printed circuit boards and integrated circuits . It builds on a preceding step, called placement, which determines the location of each active element of an IC or component on a PCB...
, and so on) is already complex and often forms its own field of study. This article, however, looks at the overall design closure process, which takes a chip from its initial design state to the final form in which all of its design constraints are met.
Introduction
Every chip starts off as someone’s idea of a good thing: "If we can make a part that performs function X, we will all be rich!" Once the concept is established, someone from marketing says "To make this chip profitably, it must cost $C and run at frequency F." Someone from manufacturing says "To meet this chip’s targets, it must have a yield of Y%." Someone from packaging says “It must fit in the P package and dissipate no more than W watts.” Eventually, the team generates an extensive list of all the constraints and objectives they must meet to manufacture a product that can be sold profitably. The management then forms a design team, which consists of chip architects, logic designers, functional verification engineers, physical designers, and timing engineers, and assigns them to create a chip to the specifications.Constraints vs Objectives
The distinction between constraints and objectives is straightforward: a constraint is a design target that must be met for the design to be successful. For example, a chip may be required to run at a specific frequency so it can interface with other components in a system. In contrast, an objective is a design target where more(or less) is better. For example, yield is generally an objective, which is maximized to lower manufacturing cost. For the purposes of design closure, the distinction between constraints and objectives is not important; this article uses the words interchangeably.
Evolution of the Design Closure Flow
Designing a chip used to be a much simpler task. In the early days of VLSI, a chip consisted of a few thousand logic circuits that performed a simple function at speeds of a few MHz. Design closure was simple: if all of the necessary circuits and wires "fit", the chip would perform the desired function.Modern design closure has grown orders of magnitude more complex. Modern logic chips can have tens to hundreds of millions of logic elements switching at speeds of several
GHz. This improvement has been driven by Moore’s law of scaling of technology, and has introduced many new design considerations. As a result, a modern VLSI designer must consider the performance of a chip against a list of dozens of design constraints and objectives including performance, power, signal integrity
Signal integrity
Signal integrity or SI is a set of measures of the quality of an electrical signal. In digital electronics, a stream of binary values is represented by a voltage waveform. However, digital signals are fundamentally analog in nature, and all signals are subject to effects such as noise,...
, reliability, and yield. In response to this growing list of constraints, the design closure flow has evolved from a simple linear list of tasks to a very complex, highly iterative flow such as the following simplified ASIC design flow:
Reference ASIC Design Flow
- Concept phase: Functional objectives and architecture of a chip are developed.
- Logic design: Architecture is implemented in a register transfer level (RTL) language, then simulated to verify that it performs the desired functions. This includes functional verificationFunctional verificationFunctional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, and takes the...
. - Floorplanning: The RTL of the chip is assigned to gross regions of the chip, input/output (I/O) pins are assigned and large objects (arrays, cores, etc.) are placed.
- Logic synthesisLogic synthesisIn electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level , is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog...
: The RTL is mapped into a gate-level netlist in the target technology of the chip. - Design for Testability: The test structures like scan chains are inserted.
- PlacementPlacement (EDA)Placement is an essential step in electronic design automation - the portion of the physical design flow that assigns exact locations for various circuitcomponents within the chip’s core area...
: The gates in the netlist are assigned to nonoverlapping locations on the chip. - Logic/placement refinement: Iterative logical and placement transformations to close performance and power constraints.
- Clock insertionClock Distribution NetworksIn a synchronous digital system,the clock signal is used to define a timereference for the movement of data within that system. The clock distribution network distributes the clock signal from a common point to all the elements that need it.Since this function isvital to the operation of a...
: Balanced buffered clock trees are introduced into the design. - RoutingRouting (EDA)In electronic design, wire routing, commonly called simply routing, is a step in the design of printed circuit boards and integrated circuits . It builds on a preceding step, called placement, which determines the location of each active element of an IC or component on a PCB...
: The wires that connect the gates in the netlist are added. - Postwiring optimization: Remaining performance, noise, and yield violations are removed.
- Design for manufacturabilityDesign for manufacturability (IC)Achieving high-yielding designs in the state of the art, VLSI technology has become an extremely challenging task due to the miniaturization as well as the complexity of leading-edge products...
: The design is modified, where possible, to make it as easy as possible to produce. - Signoff checks: Since errors are expensive, time consuming and hard to spot, extensive error checking is the rule, making sure the mapping to logic was done correctlyFormal equivalence checkingFormal equivalence checking process is a part of electronic design automation , commonly used during the development of digital integrated circuits, to formally prove that two representations of a circuit design exhibit exactly the same behavior....
, and checking that the manufacturing rules were followed faithfullyDesign rule checkingDesign Rule Checking or Check is the area of Electronic Design Automation that determines whether the physical layout of a particular chip layout satisfies a series of recommended parameters called Design Rules...
. - TapeoutTape-outIn electronics design, tape-out or tapeout is the final result of the design cycle for integrated circuits or printed circuit boards, the point at which the artwork for the photomask of a circuit is sent for manufacture....
and mask generation: the design data is turned into photomaskPhotomaskA photomask is an opaque plate with holes or transparencies that allow light to shine through in a defined pattern. They are commonly used in photolithography.-Overview:...
s in mask data preparationMask data preparationMask data preparation is the step that translates an intended set of polygons on an integrated circuit layout into a form that can be physically written by the photomask writer. Usually this involves fracturing complex polygons into simpler shapes, often rectangles and trapezoids, that can be...
.
Evolution of design constraints
The purpose of the flow is to take a design from concept phase to working chip. The complexity of the flow is a direct result of the addition and evolution of the list of design closure constraints. To understand this evolution it is important to understand the life cycle of a design constraint. In general, design constraints influence the design flow via the following five-stage evolution:- Early warnings: Before chip issues begin occurring, academics and industry visionaries make dire predictions about the future impact of some new technology effect.
- Hardware problems: Sporadic hardware failures start showing up in the field due to the new effect. Postmanufacturing redesign and hardware re-spins are required to get the chip to function.
- Trial and error: Constraints on the effect are formulated and used to drive postdesign checking. Violations of the constraint are fixed manually.
- Find and repair: Large number of violations of the constraint drives the creation of automatic postdesign analysis and repair flows.
- Predict and prevent: Constraint checking moves earlier in the flow using predictive estimations of the effect. These drive optimizations to prevent violations of the constraint.
A good example of this evolution can be found in the signal integrity
Signal integrity
Signal integrity or SI is a set of measures of the quality of an electrical signal. In digital electronics, a stream of binary values is represented by a voltage waveform. However, digital signals are fundamentally analog in nature, and all signals are subject to effects such as noise,...
constraint. In the mid-1990s (180 nm
node), industry visionaries were describing the impending dangers of coupling noise long before chips were
failing. By the mid-late 1990s, noise problems were cropping up in advanced microprocessor designs.
By 2000, automated noise analysis tools were available and were used to guide manual fix-up. The total
number of noise problems identified by the analysis tools identified by the flow quickly became too many
to correct manually. In response, CAD companies developed the noise avoidance flows that are currently in
use in the industry.
At any point in time, the constraints in the design flow are at different stages of their life cycle. At the
time of this writing, for example, performance optimization is the most mature and is well into the fifth
phase with the widespread use of timing-driven design flows. Power- and defect-oriented yield optimization
is well into the fourth phase; power supply integrity, a type of noise constraint, is in the third phase;
circuit-limited yield optimization is in the second phase, etc. A list of the first-phase impending constraint
crises can always be found in the International Technology Roadmap for Semiconductors
International Technology Roadmap for Semiconductors
The International Technology Roadmap for Semiconductors is a set of documents produced by a group of semiconductor industry experts. These experts are representative of the sponsoring organisations which include the Semiconductor Industry Associations of the US, Europe, Japan, South Korea and...
(ITRS) 15-year-outlook technology roadmaps.
As a constraint matures in the design flow, it tends to work its way from the end of the flow to the beginning.
As it does this, it also tends to increase in complexity and in the degree that it contends with other constraints.
Constraints tend to move up in the flow due to one of the basic paradoxes of design: accuracy vs.
influence. Specifically, the earlier in a design flow a constraint is addressed, the more flexibility there is to
address the constraint. Ironically, the earlier one is in a design flow, the more difficult it is to predict compliance.
For example, an architectural decision to pipeline a logic function can have a far greater impact on
total chip performance than any amount of postrouting fix-up. At the same time, accurately predicting the
performance impact of such a change before the chip logic is synthesized, let alone placed or routed, is very
difficult. This paradox has shaped the evolution of the design closure flow in several ways. First, it requires
that the design flow is no longer composed of a linear set of discrete steps. In the early stages of VLSI it was
sufficient to break the design into discrete stages, i.e., first do logic synthesis, then do placement, then do
routing. As the number and complexity of design closure constraints has increased, the linear design flow
has broken down. In the past if there were too many timing constraint violations left after routing, it was
necessary to loop back, modify the tool settings slightly, and reexecute the previous placement steps. If the
constraints were still not met, it was necessary to reach further back in the flow and modify the chip logic
and repeat the synthesis and placement steps. This type of looping is both time consuming and unable to
guarantee convergence i.e., it is possible to loop back in the flow to correct one constraint violation only to
find that the correction induced another unrelated violation.
See also
- Timing closureTiming ClosureTiming closure is the process by which an FPGA or a VLSI design is modified to meet its timing requirements. Most of the modifications are handled by EDA tools based on directives given by a designer...
- Electronic design automationElectronic design automationElectronic design automation is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits...
- Design flow (EDA)Design flow (EDA)Design flows are the explicit combination of electronic design automation tools to accomplish the design of an integrated circuit. Moore's law has driven the entire IC implementation RTL to GDSII design flows from one which uses primarily...
- Integrated circuit designIntegrated circuit designIntegrated circuit design, or IC design, is a subset of electrical engineering and computer engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs...