Timing closure is the process by which an FPGA or a VLSI

Integrated circuit

An integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...

 design is modified to meet its timing requirements. Most of the modifications are handled by EDA

Electronic design automation

Electronic design automation is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits...

 tools based on directives given by a designer. The term is also used for the goal that is achieved, when such a design has reached the end of the flow and its timing requirements are satisfied.

The main steps of the design flow, which may be involved in this process, are logic synthesis, placement

Placement (EDA)

Placement is an essential step in electronic design automation - the portion of the physical design flow that assigns exact locations for various circuitcomponents within the chip’s core area...

, clock-tree synthesis and routing

Routing (EDA)

In electronic design, wire routing, commonly called simply routing, is a step in the design of printed circuit boards and integrated circuits . It builds on a preceding step, called placement, which determines the location of each active element of an IC or component on a PCB...

. With present technologies all of them need to be timing-aware for a design to properly meet its timing requirements, but with technologies in the range of the micrometre only logic synthesis EDA tools had such a prerequisite.

Nevertheless, even if timing-awareness was extended to all these steps starting from well-established principles used for logic synthesis, the two phases, logic and physical, of the timing closure process are conventionally handled by different design teams and different EDA tools. Design Compiler by Synopsys, Encounter RTL Compiler by Cadence Design Systems and BlastCreate by Magma Design Automation are examples of logic synthesis tools. IC Compiler by Synopsys, SoC Encounter by Cadence Design Systems and Blast Fusion by Magma Design Automation are examples of tools capable of timing-aware placement, clock tree synthesis and routing and therefore used for physical timing closure

Physical timing closure

Physical timing closure is the process by which an FPGA or a VLSI design with a physical representation is modified to meet its timing requirements. Most of the modifications are handled by EDA tools based on directives given by a designer...

.

A timing requirement needs to be translated into a static timing

Static timing analysis

Static Timing Analysis is a method of computing the expected timing of a digital circuit without requiring simulation.High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate...

 constraint for an EDA tool to be able to handle it.

See also

• Design closure
  Design closure
  Design closure is the process by which a VLSI design is modified from its initial description to meet a growing list of design constraints and objectives....
  
  
• Electronic design automation
  Electronic design automation
  Electronic design automation is a category of software tools for designing electronic systems such as printed circuit boards and integrated circuits...
  
  
• Design flow (EDA)
  Design flow (EDA)
  Design flows are the explicit combination of electronic design automation tools to accomplish the design of an integrated circuit. Moore's law has driven the entire IC implementation RTL to GDSII design flows from one which uses primarily...
  
  
• Integrated circuit design
  Integrated circuit design
  Integrated circuit design, or IC design, is a subset of electrical engineering and computer engineering, encompassing the particular logic and circuit design techniques required to design integrated circuits, or ICs...
  
  
• Physical timing closure
  Physical timing closure
  Physical timing closure is the process by which an FPGA or a VLSI design with a physical representation is modified to meet its timing requirements. Most of the modifications are handled by EDA tools based on directives given by a designer...
  
  
• Static timing analysis
  Static timing analysis
  Static Timing Analysis is a method of computing the expected timing of a digital circuit without requiring simulation.High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate...
  
  

External links

• Design Compiler by Synopsys
• Encounter RTL Compiler by Cadence Design Systems
• BlastCreate by Magma Design Automation
• IC Compiler by Synopsys
• SoC Encounter by Cadence Design Systems
• Blast Fusion by Magma Design Automation