Kendall Square Research
Encyclopedia
Kendall Square Research (KSR) was a supercomputer
company headquartered originally in Kendall Square
in Cambridge, Massachusetts
in 1986, near MIT
. It was co-founded by Steven Frank and Henry Burkhardt III
, who had previously helped found Data General
and Encore Computer
and was one of the original team that designed the PDP-8
. KSR produced two models of supercomputer, the KSR1 and KSR2.
, a Unix
variant, with programs compiled by a KSR-specific port of the Greenhills C and FORTRAN compilers. The architecture
was shared memory
implemented as an cache only memory architecture
or "COMA". Being all cache, memory dynamically migrated and replicated in a coherent manner based on access pattern of individual processors. The processors were arranged in a hierarchy of rings, and the operating system mediated process migration and device access. Instruction decode was hardwired, and pipelining was used. Each KSR1 processor was a custom 64-bit
RISC CPU clocked at 20 MHz and capable of peak output of 20 MIPS and 40 MFLOPS. Up to 1088 of these processors could be arranged in a single system, with a minimum of eight. The KSR2 doubled the clock rate to 40 MHz and supported over 5000 processors.
The KSR-1 chipset was fabricated by Sharp Corporation
while the KSR-2 chipset was built by Hewlett-Packard
.
, addressed the massively parallel database market for commercial applications. The KSR-1 and -2 supported Micro Focus COBOL
and C
/C++ programming languages, as well as the Oracle PRDBMS and the MATISSE OODBMS from ADB, Inc. Their own product, the KSR Query Decomposer, complemented the functionality of the Oracle product for SQL
uses. The TUXEDO transaction monitor for OLTP was also provided. The KAP program (Kuck & Associate Preprocessor) provided for pre-processing for source code
analysis
and parallelization. The runtime environment was termed PRESTO, and was a POSIX
compliant multithreading
manager.
. These chips were: the Cell Execution Unit, the floating point unit
, the arithmetic logic unit
, and the external I/O unit (XIO). The CEU handled instruction fetch (two per clock), and all operations involving memory, such as loads and stores. 40 bit addresses were used, going to full 64-bit addresses later. The integer unit had 32, 64-bit-wide registers. The floating point
unit is discussed below. The XIO had the capability of 30 MB
/s throughput to I/O devices. It included 64 control and data registers.
The KSR processor was a 2-wide VLIW, with instructions of 6 types: memory reference (load and store), execute, control flow, memory control, I/O, and inserted. Execute instructions included arithmetic, logical, and type conversion. They were usually triadic register
in format. Control flow refers to branches and jumps. Branch instructions were two cycles. The programmer (or compiler) could implicitly control the "quashing" behavior of the subsequent two instructions that would be initiated during the branch. The choices were: always retain the results, retain results if branch test is true, or retain results if branch test is false. Memory control provided synchronization primitives. I/O instructions were provided. Inserted instructions were forced into a flow by a coprocessor
. Inserted load and store were used for DMA
transfers. Inserted memory instructions were used to maintain cache coherency. New coprocessors could be interfaced with the inserted instruction mechanism. IEEE standard floating point arithmetic was supported. Sixty-four 64-bit wide registers were included.
The following example of KSR assembly performs an indirect procedure call to an address held in the procedure's constant block, saving the return address in register
means wrong values are sometimes loaded.
In the KSR design, all of the memory was treated as cache. The original design called for no "home" location, to reduce storage overheads; however, it occasionally deadlocked, so shipping machines used home locations. The "home" location was locked to a node, thus doubling the physical memory used by most private data, and also reducing the node memory that could be used as cache. A Harvard style
, separate bus for instructions and memory was used. Each node board contained 256 kB
of I-cache and D-cache, essentially primary cache. At each node was 32 MB of memory for main cache. The system level architecture was shared virtual memory, which was physically distributed in the machine. The programmer or application only saw one contiguous address space, which was spanned by a 40-bit address. Traffic between nodes traveled at up to 4 gigabytes per second. The 32 megabytes per node, in aggregate, formed the physical memory of the machine.
Specialized input/output
processors could be used in the system, providing scalable I/O. A 1088 node KSR1 could have 510 I/O channels with an aggregate in excess of 15 GB
/s. Interfaces such as Ethernet
, FDDI, and HIPPI
were supported.
, 170 Tracer Lane in Waltham, Massachusetts.
KSR refocused its efforts from the scientific to the commercial marketplace, with emphasis on parallel relational databases and OLTP operations. It then got out of the hardware business, but continued to market some of its data warehousing and analysis software products.
The first KSR1 system was installed in 1991. With new processor hardware, new memory hardware and a novel memory architecture, a new compiler port, a new port of a relatively new operating system, and exposed memory hazards, early systems were noted for frequent system crashes. KSR called their COMA
by the trade name "Allcache"; reliability problems with early systems earned it the nickname "Allcrash", although memory was not necessarily the root cause of crashes. A few KSR1 models were sold, and as the KSR2 was being rolled out, the company collapsed amid accounting irregularities involving the overstatement of revenue.
KSR used a proprietary processor because 64-bit processors were not commercially available. However, this put the small company in the difficult position of doing both processor design and system design. The KSR processors were introduced in 1991 at 20 MHz and 40 MFlops. At that time, the 32-bit Intel 80486 ran at 50 MHz and 50 MFlops. When the 64-bit DEC Alpha
was introduced in 1992, it ran at up to 192 MHz and 192 MFlops, while the 1992 KSR2 ran at 40 MHz and 80 MFlops.
One customer of the KSR2, the Pacific Northwest National Laboratory
, a United States Department of Energy
facility, purchased an enormous number of spare parts, and kept their machines running for years after the demise of KSR.
KSR, along with many of its competitors (see below) went bankrupt during the collapse of the supercomputer market in the early-1990s. KSR went out of business in February 1994 when their stock was delisted from the stock exchange.
, in addition to various old-line (and still surviving) companies like IBM, Intel, and Sun Microsystems
.
Supercomputer
A supercomputer is a computer at the frontline of current processing capacity, particularly speed of calculation.Supercomputers are used for highly calculation-intensive tasks such as problems including quantum physics, weather forecasting, climate research, molecular modeling A supercomputer is a...
company headquartered originally in Kendall Square
Kendall Square
Kendall Square is a neighborhood in Cambridge, Massachusetts, with the "square" itself at the intersection of Main Street, Broadway, Wadsworth Street, and Third Street...
in Cambridge, Massachusetts
Cambridge, Massachusetts
Cambridge is a city in Middlesex County, Massachusetts, United States, in the Greater Boston area. It was named in honor of the University of Cambridge in England, an important center of the Puritan theology embraced by the town's founders. Cambridge is home to two of the world's most prominent...
in 1986, near MIT
Massachusetts Institute of Technology
The Massachusetts Institute of Technology is a private research university located in Cambridge, Massachusetts. MIT has five schools and one college, containing a total of 32 academic departments, with a strong emphasis on scientific and technological education and research.Founded in 1861 in...
. It was co-founded by Steven Frank and Henry Burkhardt III
Henry Burkhardt III
Henry Burkhardt III was born in Ann Arbor, Michigan, USA, grew up in South Hadley, Massachusetts, and was schooled there. He graduated from Phillips Exeter Academy and attended Princeton University. He began his career as a programmer at Digital Equipment Corporation...
, who had previously helped found Data General
Data General
Data General was one of the first minicomputer firms from the late 1960s. Three of the four founders were former employees of Digital Equipment Corporation. Their first product, the Data General Nova, was a 16-bit minicomputer...
and Encore Computer
Encore Computer
Encore Computer was an early pioneer in the parallel computing market, based in Marlborough, Massachusetts. Although offering a number of system designs beginning in 1985, they were never as well known as other companies in this field such as Pyramid Technology, Alliant, and the most similar...
and was one of the original team that designed the PDP-8
PDP-8
The 12-bit PDP-8 was the first successful commercial minicomputer, produced by Digital Equipment Corporation in the 1960s. DEC introduced it on 22 March 1965, and sold more than 50,000 systems, the most of any computer up to that date. It was the first widely sold computer in the DEC PDP series of...
. KSR produced two models of supercomputer, the KSR1 and KSR2.
Technology
The KSR systems ran a specially customized version of the OSF/1 operating systemOperating system
An operating system is a set of programs that manage computer hardware resources and provide common services for application software. The operating system is the most important type of system software in a computer system...
, a Unix
Unix
Unix is a multitasking, multi-user computer operating system originally developed in 1969 by a group of AT&T employees at Bell Labs, including Ken Thompson, Dennis Ritchie, Brian Kernighan, Douglas McIlroy, and Joe Ossanna...
variant, with programs compiled by a KSR-specific port of the Greenhills C and FORTRAN compilers. The architecture
Computer architecture
In computer science and engineering, computer architecture is the practical art of selecting and interconnecting hardware components to create computers that meet functional, performance and cost goals and the formal modelling of those systems....
was shared memory
Shared memory
In computing, shared memory is memory that may be simultaneously accessed by multiple programs with an intent to provide communication among them or avoid redundant copies. Depending on context, programs may run on a single processor or on multiple separate processors...
implemented as an cache only memory architecture
Cache only memory architecture
Cache only memory architecture is a computer memory organization for use in multiprocessors in which the local memories at each node are used as cache. This is in contrast to using the local memories as actual main memory, as in NUMA organizations.In NUMA, each address in the global address...
or "COMA". Being all cache, memory dynamically migrated and replicated in a coherent manner based on access pattern of individual processors. The processors were arranged in a hierarchy of rings, and the operating system mediated process migration and device access. Instruction decode was hardwired, and pipelining was used. Each KSR1 processor was a custom 64-bit
64-bit
64-bit is a word size that defines certain classes of computer architecture, buses, memory and CPUs, and by extension the software that runs on them. 64-bit CPUs have existed in supercomputers since the 1970s and in RISC-based workstations and servers since the early 1990s...
RISC CPU clocked at 20 MHz and capable of peak output of 20 MIPS and 40 MFLOPS. Up to 1088 of these processors could be arranged in a single system, with a minimum of eight. The KSR2 doubled the clock rate to 40 MHz and supported over 5000 processors.
The KSR-1 chipset was fabricated by Sharp Corporation
Sharp Corporation
is a Japanese multinational corporation that designs and manufactures electronic products. Headquartered in Abeno-ku, Osaka, Japan, Sharp employs more than 55,580 people worldwide as of June 2011. The company was founded in September 1912 and takes its name from one of its founder's first...
while the KSR-2 chipset was built by Hewlett-Packard
Hewlett-Packard
Hewlett-Packard Company or HP is an American multinational information technology corporation headquartered in Palo Alto, California, USA that provides products, technologies, softwares, solutions and services to consumers, small- and medium-sized businesses and large enterprises, including...
.
Software
Besides the traditional scientific applications, KSR, in conjunction with Oracle CorporationOracle Corporation
Oracle Corporation is an American multinational computer technology corporation that specializes in developing and marketing hardware systems and enterprise software products – particularly database management systems...
, addressed the massively parallel database market for commercial applications. The KSR-1 and -2 supported Micro Focus COBOL
COBOL
COBOL is one of the oldest programming languages. Its name is an acronym for COmmon Business-Oriented Language, defining its primary domain in business, finance, and administrative systems for companies and governments....
and C
C (programming language)
C is a general-purpose computer programming language developed between 1969 and 1973 by Dennis Ritchie at the Bell Telephone Laboratories for use with the Unix operating system....
/C++ programming languages, as well as the Oracle PRDBMS and the MATISSE OODBMS from ADB, Inc. Their own product, the KSR Query Decomposer, complemented the functionality of the Oracle product for SQL
SQL
SQL is a programming language designed for managing data in relational database management systems ....
uses. The TUXEDO transaction monitor for OLTP was also provided. The KAP program (Kuck & Associate Preprocessor) provided for pre-processing for source code
Source code
In computer science, source code is text written using the format and syntax of the programming language that it is being written in. Such a language is specially designed to facilitate the work of computer programmers, who specify the actions to be performed by a computer mostly by writing source...
analysis
Analysis
Analysis is the process of breaking a complex topic or substance into smaller parts to gain a better understanding of it. The technique has been applied in the study of mathematics and logic since before Aristotle , though analysis as a formal concept is a relatively recent development.The word is...
and parallelization. The runtime environment was termed PRESTO, and was a POSIX
POSIX
POSIX , an acronym for "Portable Operating System Interface", is a family of standards specified by the IEEE for maintaining compatibility between operating systems...
compliant multithreading
Thread (computer science)
In computer science, a thread of execution is the smallest unit of processing that can be scheduled by an operating system. The implementation of threads and processes differs from one operating system to another, but in most cases, a thread is contained inside a process...
manager.
Hardware
The KSR-1 processor was implemented as a four-chip set in 1.2 micrometer CMOSCMOS
Complementary metal–oxide–semiconductor is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits...
. These chips were: the Cell Execution Unit, the floating point unit
Floating point unit
A floating-point unit is a part of a computer system specially designed to carry out operations on floating point numbers. Typical operations are addition, subtraction, multiplication, division, and square root...
, the arithmetic logic unit
Arithmetic logic unit
In computing, an arithmetic logic unit is a digital circuit that performs arithmetic and logical operations.The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers...
, and the external I/O unit (XIO). The CEU handled instruction fetch (two per clock), and all operations involving memory, such as loads and stores. 40 bit addresses were used, going to full 64-bit addresses later. The integer unit had 32, 64-bit-wide registers. The floating point
Floating point
In computing, floating point describes a method of representing real numbers in a way that can support a wide range of values. Numbers are, in general, represented approximately to a fixed number of significant digits and scaled using an exponent. The base for the scaling is normally 2, 10 or 16...
unit is discussed below. The XIO had the capability of 30 MB
Megabyte
The megabyte is a multiple of the unit byte for digital information storage or transmission with two different values depending on context: bytes generally for computer memory; and one million bytes generally for computer storage. The IEEE Standards Board has decided that "Mega will mean 1 000...
/s throughput to I/O devices. It included 64 control and data registers.
The KSR processor was a 2-wide VLIW, with instructions of 6 types: memory reference (load and store), execute, control flow, memory control, I/O, and inserted. Execute instructions included arithmetic, logical, and type conversion. They were usually triadic register
Processor register
In computer architecture, a processor register is a small amount of storage available as part of a CPU or other digital processor. Such registers are addressed by mechanisms other than main memory and can be accessed more quickly...
in format. Control flow refers to branches and jumps. Branch instructions were two cycles. The programmer (or compiler) could implicitly control the "quashing" behavior of the subsequent two instructions that would be initiated during the branch. The choices were: always retain the results, retain results if branch test is true, or retain results if branch test is false. Memory control provided synchronization primitives. I/O instructions were provided. Inserted instructions were forced into a flow by a coprocessor
Coprocessor
A coprocessor is a computer processor used to supplement the functions of the primary processor . Operations performed by the coprocessor may be floating point arithmetic, graphics, signal processing, string processing, or encryption. By offloading processor-intensive tasks from the main processor,...
. Inserted load and store were used for DMA
Direct memory access
Direct memory access is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit ....
transfers. Inserted memory instructions were used to maintain cache coherency. New coprocessors could be interfaced with the inserted instruction mechanism. IEEE standard floating point arithmetic was supported. Sixty-four 64-bit wide registers were included.
The following example of KSR assembly performs an indirect procedure call to an address held in the procedure's constant block, saving the return address in register
c14. It also saves the frame pointer, loads integer regstier zero with the value 3, and increments integer register 31 without changing the condition codes. Most instructions have a delay slot of 2 cycles and the delay slots are not interlocked, so must be scheduled explicitly, else the resulting hazardHazard
A hazard is a situation that poses a level of threat to life, health, property, or environment. Most hazards are dormant or potential, with only a theoretical risk of harm; however, once a hazard becomes "active", it can create an emergency situation. A hazard does not exist when it is not...
means wrong values are sometimes loaded.
finop ; movb8_8 %i2,%c10
finop ; cxnop
finop ; cxnop
add8.ntr 75,%i31,%i31 ; ld8 8(%c10),%c4
finop ; st8 %fp,504(%sp)
finop ; cxnop
movi8 3, %i0 ; jsr %c14,16(%c4)
In the KSR design, all of the memory was treated as cache. The original design called for no "home" location, to reduce storage overheads; however, it occasionally deadlocked, so shipping machines used home locations. The "home" location was locked to a node, thus doubling the physical memory used by most private data, and also reducing the node memory that could be used as cache. A Harvard style
Harvard architecture
The Harvard architecture is a computer architecture with physically separate storage and signal pathways for instructions and data. The term originated from the Harvard Mark I relay-based computer, which stored instructions on punched tape and data in electro-mechanical counters...
, separate bus for instructions and memory was used. Each node board contained 256 kB
Kilobyte
The kilobyte is a multiple of the unit byte for digital information. Although the prefix kilo- means 1000, the term kilobyte and symbol KB have historically been used to refer to either 1024 bytes or 1000 bytes, dependent upon context, in the fields of computer science and information...
of I-cache and D-cache, essentially primary cache. At each node was 32 MB of memory for main cache. The system level architecture was shared virtual memory, which was physically distributed in the machine. The programmer or application only saw one contiguous address space, which was spanned by a 40-bit address. Traffic between nodes traveled at up to 4 gigabytes per second. The 32 megabytes per node, in aggregate, formed the physical memory of the machine.
Specialized input/output
Input/output
In computing, input/output, or I/O, refers to the communication between an information processing system , and the outside world, possibly a human, or another information processing system. Inputs are the signals or data received by the system, and outputs are the signals or data sent from it...
processors could be used in the system, providing scalable I/O. A 1088 node KSR1 could have 510 I/O channels with an aggregate in excess of 15 GB
Gigabyte
The gigabyte is a multiple of the unit byte for digital information storage. The prefix giga means 109 in the International System of Units , therefore 1 gigabyte is...
/s. Interfaces such as Ethernet
Ethernet
Ethernet is a family of computer networking technologies for local area networks commercially introduced in 1980. Standardized in IEEE 802.3, Ethernet has largely replaced competing wired LAN technologies....
, FDDI, and HIPPI
HIPPI
HIPPI is a computer bus for the attachment of high speed storage devices to supercomputers. It was popular in the late 1980s and into the mid-to-late 1990s, but has since been replaced by ever-faster standard interfaces like SCSI and Fibre Channel.The first HIPPI standard defined a 50-wire...
were supported.
History
As the company scaled up quickly to enter production, they moved in the late 1980s to Waltham, MassachusettsWaltham, Massachusetts
Waltham is a city in Middlesex County, Massachusetts, United States, was an early center for the labor movement, and major contributor to the American Industrial Revolution. The original home of the Boston Manufacturing Company, the city was a prototype for 19th century industrial city planning,...
, 170 Tracer Lane in Waltham, Massachusetts.
KSR refocused its efforts from the scientific to the commercial marketplace, with emphasis on parallel relational databases and OLTP operations. It then got out of the hardware business, but continued to market some of its data warehousing and analysis software products.
The first KSR1 system was installed in 1991. With new processor hardware, new memory hardware and a novel memory architecture, a new compiler port, a new port of a relatively new operating system, and exposed memory hazards, early systems were noted for frequent system crashes. KSR called their COMA
Cache only memory architecture
Cache only memory architecture is a computer memory organization for use in multiprocessors in which the local memories at each node are used as cache. This is in contrast to using the local memories as actual main memory, as in NUMA organizations.In NUMA, each address in the global address...
by the trade name "Allcache"; reliability problems with early systems earned it the nickname "Allcrash", although memory was not necessarily the root cause of crashes. A few KSR1 models were sold, and as the KSR2 was being rolled out, the company collapsed amid accounting irregularities involving the overstatement of revenue.
KSR used a proprietary processor because 64-bit processors were not commercially available. However, this put the small company in the difficult position of doing both processor design and system design. The KSR processors were introduced in 1991 at 20 MHz and 40 MFlops. At that time, the 32-bit Intel 80486 ran at 50 MHz and 50 MFlops. When the 64-bit DEC Alpha
DEC Alpha
Alpha, originally known as Alpha AXP, is a 64-bit reduced instruction set computer instruction set architecture developed by Digital Equipment Corporation , designed to replace the 32-bit VAX complex instruction set computer ISA and its implementations. Alpha was implemented in microprocessors...
was introduced in 1992, it ran at up to 192 MHz and 192 MFlops, while the 1992 KSR2 ran at 40 MHz and 80 MFlops.
One customer of the KSR2, the Pacific Northwest National Laboratory
Pacific Northwest National Laboratory
Pacific Northwest National Laboratory is one of the United States Department of Energy National Laboratories, managed by the Department of Energy's Office of Science. The main campus of the laboratory is in Richland, Washington....
, a United States Department of Energy
United States Department of Energy
The United States Department of Energy is a Cabinet-level department of the United States government concerned with the United States' policies regarding energy and safety in handling nuclear material...
facility, purchased an enormous number of spare parts, and kept their machines running for years after the demise of KSR.
KSR, along with many of its competitors (see below) went bankrupt during the collapse of the supercomputer market in the early-1990s. KSR went out of business in February 1994 when their stock was delisted from the stock exchange.
Competition
KSR's competitors included Thinking Machines and Meiko ScientificMeiko Scientific
Meiko Scientific Ltd. was a British supercomputer company based in Bristol, founded by members of the design team working on the INMOS transputer microprocessor.-History:...
, in addition to various old-line (and still surviving) companies like IBM, Intel, and Sun Microsystems
Sun Microsystems
Sun Microsystems, Inc. was a company that sold :computers, computer components, :computer software, and :information technology services. Sun was founded on February 24, 1982...
.