Memory rank
Encyclopedia
A memory rank is a set of DRAMs
connected to the same chip select
, and which are therefore accessed simultaneously. In practice they also share all of the other command and control signals, and only the data pins for each DRAM are separate (but the data pins are shared across ranks).
The term “rank” was created and defined by JEDEC
, the memory industry standards group. On a DDR
, DDR2
, or DDR3
memory module
, each rank has a 64-bit wide data bus (with an optional extra 8-bit ECC on some DIMMs). The number of physical DRAMs depends on their individual widths. For example, a rank of x8 (8-bit) DRAMs would consist of 8 physical chips (plus one for ECC), but a rank of x4 (4-bit) DRAMs would consist of 16 physical chips (plus two for ECC). Multiple ranks can coexist on a single DIMM, and modern DIMMs can consist of one rank (single rank), two ranks (dual rank), four ranks (quad rank), or eight ranks (octal rank).
There is little difference between a dual rank UDIMM
and two single rank UDIMMs in the same memory channel, other than that the DRAMs reside on different PCBs
. The electrical connections between the memory controller
and the DRAMs are almost identical (with the possible exception of which chip selects go to which ranks). Increasing the number of ranks per DIMM increases memory density in the channel, but does not enhance performance; too many ranks in the channel can cause excess loading and decrease the speed of the channel. DRAM load can be lessened by using registered memory
.
Memory operations to a single rank are generally faster than memory operations that span ranks, as individual ranks have different flight times and may require the memory controller to insert small delays when switching between ranks. However, modern memory controllers attempt to spread memory operations across ranks for power and thermal reasons.
Dram
Dram or DRAM may refer to:As a unit of measure:* Dram , an imperial unit of mass and volume* Armenian dram, a monetary unit* Dirham, a unit of currency in several Arab nationsOther uses:...
connected to the same chip select
Chip select
Chip select or slave select is the name of a control line in digital electronics used to select one chip out of several connected to the same computer bus usually utilizing the three-state logic....
, and which are therefore accessed simultaneously. In practice they also share all of the other command and control signals, and only the data pins for each DRAM are separate (but the data pins are shared across ranks).
The term “rank” was created and defined by JEDEC
JEDEC
The JEDEC Solid State Technology Association, formerly known as the Joint Electron Devices Engineering Council , is an independent semiconductor engineering trade organization and standardization body...
, the memory industry standards group. On a DDR
DDR SDRAM
Double data rate synchronous dynamic random access memory is a class of memory integrated circuits used in computers. DDR SDRAM has been superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which are either forward or backward compatible with DDR SDRAM, meaning that DDR2 or DDR3 memory modules...
, DDR2
DDR2 SDRAM
DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM...
, or DDR3
DDR3 SDRAM
In computing, DDR3 SDRAM, an abbreviation for double data rate type three synchronous dynamic random access memory, is a modern kind of dynamic random access memory with a high bandwidth interface. It is one of several variants of DRAM and associated interface techniques used since the early 1970s...
memory module
DIMM
A DIMM or dual in-line memory module, comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers...
, each rank has a 64-bit wide data bus (with an optional extra 8-bit ECC on some DIMMs). The number of physical DRAMs depends on their individual widths. For example, a rank of x8 (8-bit) DRAMs would consist of 8 physical chips (plus one for ECC), but a rank of x4 (4-bit) DRAMs would consist of 16 physical chips (plus two for ECC). Multiple ranks can coexist on a single DIMM, and modern DIMMs can consist of one rank (single rank), two ranks (dual rank), four ranks (quad rank), or eight ranks (octal rank).
There is little difference between a dual rank UDIMM
Unbuffered memory
Unbuffered memory is RAM where there is no hardware register between the memory controller and the RAM chips. Unbuffered memory is the opposite of registered memory. Registered memory is more stable, one clock cycle slower, and more expensive than unbuffered memory...
and two single rank UDIMMs in the same memory channel, other than that the DRAMs reside on different PCBs
Printed circuit board
A printed circuit board, or PCB, is used to mechanically support and electrically connect electronic components using conductive pathways, tracks or signal traces etched from copper sheets laminated onto a non-conductive substrate. It is also referred to as printed wiring board or etched wiring...
. The electrical connections between the memory controller
Memory controller
The memory controller is a digital circuit which manages the flow of data going to and from the main memory. It can be a separate chip or integrated into another chip, such as on the die of a microprocessor...
and the DRAMs are almost identical (with the possible exception of which chip selects go to which ranks). Increasing the number of ranks per DIMM increases memory density in the channel, but does not enhance performance; too many ranks in the channel can cause excess loading and decrease the speed of the channel. DRAM load can be lessened by using registered memory
Registered memory
Registered memory modules have a register between the DRAM modules and the system's memory controller. They place less electrical load on the memory controller and allow single systems to remain stable with more memory modules than they would have otherwise...
.
Memory operations to a single rank are generally faster than memory operations that span ranks, as individual ranks have different flight times and may require the memory controller to insert small delays when switching between ranks. However, modern memory controllers attempt to spread memory operations across ranks for power and thermal reasons.