DDR3 SDRAM
Encyclopedia
In computing
, DDR3 SDRAM, an abbreviation for double data rate
type three synchronous dynamic random access memory
, is a modern kind of dynamic random access memory
(DRAM) with a high bandwidth
interface. It is one of several variants of DRAM and associated interface techniques used since the early 1970s. DDR3 SDRAM is neither forward
nor backward compatible
with any earlier type of random access memory (RAM) due to different signaling voltages, timings, and other factors.
DDR3 is a DRAM interface specification. The actual DRAM arrays that store the data are similar to earlier types, with similar performance.
The primary benefit of DDR3 SDRAM over its immediate predecessor, DDR2 SDRAM
, is its ability to transfer data at twice the rate (eight times the speed of its internal memory arrays), enabling higher bandwidth or peak data rates. With two transfers per cycle of a quadrupled clock, a 64-bit
wide DDR3 module may achieve a transfer rate of up to 64 times the memory clock speed in megabyte
s per second (MB/s). With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR3 SDRAM gives a maximum transfer rate of 6400 MB/s. In addition, the DDR3 standard permits chip capacities of up to 8 gigabit
s.
modules due to DDR3's 1.5 V supply voltage, compared to DDR2's 1.8 V or DDR's 2.5 V. The 1.5 V supply voltage works well with the 90 nanometer
fabrication technology used in the original DDR3 chips. Some manufacturers further propose using "dual-gate" transistors
to reduce leakage
of current.
According to JEDEC
the maximum recommended voltage is 1.575 volts and should be considered the absolute maximum when memory stability is the foremost consideration, such as in servers or other mission critical devices. In addition, JEDEC states that memory modules must withstand up to 1.975 volts before incurring permanent damage, although they are not required to function correctly at that level.
Two low voltage DDR3 standards have been introduced by JEDEC. The DDR3L standard operates with a default voltage of 1.35V, using at least 15% less power than standard voltage (1.5V) DDR3. Modules with DDR3L are labeled ’’PC3L’’, and examples include DDR3L‐800, DDR3L‐1066, DDR3L‐1333, and DDR3L‐1600. The DDR3U standard operates with a default voltage of 1.25V, and modules are labelled ’’PC3U’’.
The main benefit of DDR3 comes from the higher bandwidth made possible by DDR3's 8-burst-deep prefetch buffer
, in contrast to DDR2's 4-burst-deep or DDR
's 2-burst-deep prefetch buffer.
DDR3 modules can transfer data at a rate of 800–2133 MT/s using both rising and falling edges
of a 400–1066 MHz I/O clock. Sometimes, a vendor may misleadingly advertise the I/O clock rate by labeling the MT/s as MHz. The MT/s is normally twice that of MHz by double sampling, one on the rising clock edge, and the other, on the falling. In comparison, DDR2's current range of data transfer rates is 400–1066 MT/s using a 200–533 MHz I/O clock, and DDR's range is 200–400 MT/s based on a 100–200 MHz I/O clock. High-performance graphics was an initial driver of such bandwidth requirements, where high bandwidth data transfer between framebuffer
s is required.
DDR3 does use the same electric signaling standard as DDR
and DDR2
, Stub Series Terminated Logic
, albeit at different timings and voltages. Specifically DDR3 uses SSTL_15.
DDR3 prototypes were announced in early 2005. Products in the form of motherboards appeared on the market in June 2007 based on Intel
's P35 "Bearlake" chipset
with DIMMs at bandwidths up to DDR3-1600 (PC3-12800). The Intel Core i7, released in November 2008, connects directly to memory rather than via a chipset. The Core i7 supports only DDR3. AMD
's first socket AM3
Phenom II
X4 processors, released in February 2009, were their first to support DDR3.
DDR3 DIMM
s have 240 pins and are electrically incompatible with DDR2. The two are prevented from being accidentally interchanged by different key notch positions on the DIMMs. DDR3 SO-DIMM
s have 204 pins.
GDDR3
memory, sometimes incorrectly referred to as "DDR3" due to its similar name, is an entirely different technology, as it is designed for use in graphics cards and technologically based on DDR2 SDRAM
.
for a JEDEC DDR2 device were 5-5-5-15, some standard latencies for JEDEC DDR3 devices include 7-7-7-20 for DDR3-1066 and 8-8-8-24 for DDR3-1333.
DDR3 latencies are numerically higher because the I/O bus clock cycles by which they are measured are shorter; the actual time interval is similar to DDR2 latencies (around 10 ns). There is some improvement because DDR3 generally uses more recent manufacturing processes, but this is not directly caused by the change to DDR3.
As with earlier memory generations, faster DDR3 memory became available after the release of the initial versions. DDR3-2000 memory with 9-9-9-28 latency (9 ns) was available in time to coincide with the Intel Core i7 release. CAS latency
of 9 at 1000 MHz (DDR3-2000) is 9 ns, while CAS latency of 7 at 667 MHz (DDR3-1333) is 10.5 ns.
(CAS / Frequency (MHz)) × 1000 = X ns
Example:
(7 / 667) × 1000 = 10.4948 ns
specifications for DDR3 SDRAM.
* optional
CL
- Clock cycles between sending a column address to the memory and the beginning of the data in response
tRCD - Clock cycles between row activate and reads/writes
tRP - Clock cycles between row precharge and activate
Fractional frequencies are normally rounded down, but rounding up to -667 is common due to the exact number being -666⅔ and rounding to the nearest whole number. Some manufacturers also round to a certain precision or round up instead, as such PC3-10666 memory could also be listed as PC3-10600 or PC3-10700 despite operating at the same frequency.
Note: All above listed are specified by JEDEC
as JESD79-3D. All RAM data rates in-between or above these listed specifications are not standardized by JEDEC—often they are simply manufacturer optimizations using higher-tolerance or overvolted chips. Of these non-standard specifications, the highest reported speed reached was equivalent to DDR3-2544 as of May 2010.
DDR3-xxx denotes data transfer rate, and describes raw DDR chips, whereas PC3-xxxx denotes theoretical bandwidth (with the last two digits truncated), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR3 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.
In addition to bandwidth and capacity variants, modules can
DDR3 modules
Technological advantages compared to DDR2
Committee responsible for creating the DDR3 standard, stated that DDR3 had been under development for "about 3 years". DDR3 was launched in 2007, however sales were not expected to overtake DDR2 until the end of 2009, or possibly early 2010, according to Intel strategist Carlos Weissenberg, speaking during the early part of their roll-out in August 2008 (the same timescale for market penetration had been stated by market intelligence
company DRAMeXchange over a year earlier in April 2007. and by Desi Rhoden in 2005) The primary driving force behind the increased usage of DDR3 has been new Core i7 processors from Intel and Phenom II
processors from AMD, both of which have internal memory controllers: the latter recommends DDR3, the former requires it. IDC
stated in January 2009 that DDR3 sales will account for 29 percent of the total DRAM units sold in 2009, rising to 72% by 2011.
. Some manufacturers have already demonstrated DDR4 chips for testing purposes.
Computing
Computing is usually defined as the activity of using and improving computer hardware and software. It is the computer-specific part of information technology...
, DDR3 SDRAM, an abbreviation for double data rate
Double data rate
In computing, a computer bus operating with double data rate transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition....
type three synchronous dynamic random access memory
Synchronous dynamic random access memory
Synchronous dynamic random access memory is dynamic random access memory that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs...
, is a modern kind of dynamic random access memory
Dynamic random access memory
Dynamic random-access memory is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either charged or discharged; these two states are taken to represent the two values of a bit, conventionally called 0 and 1...
(DRAM) with a high bandwidth
Bandwidth (computing)
In computer networking and computer science, bandwidth, network bandwidth, data bandwidth, or digital bandwidth is a measure of available or consumed data communication resources expressed in bits/second or multiples of it .Note that in textbooks on wireless communications, modem data transmission,...
interface. It is one of several variants of DRAM and associated interface techniques used since the early 1970s. DDR3 SDRAM is neither forward
Forward compatibility
Forward compatibility or upward compatibility is a compatibility concept for systems design, as e.g. backward compatibility. Forward compatibility aims at the ability of a design to gracefully accept input intended for later versions of itself...
nor backward compatible
Backward compatibility
In the context of telecommunications and computing, a device or technology is said to be backward or downward compatible if it can work with input generated by an older device...
with any earlier type of random access memory (RAM) due to different signaling voltages, timings, and other factors.
DDR3 is a DRAM interface specification. The actual DRAM arrays that store the data are similar to earlier types, with similar performance.
The primary benefit of DDR3 SDRAM over its immediate predecessor, DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM...
, is its ability to transfer data at twice the rate (eight times the speed of its internal memory arrays), enabling higher bandwidth or peak data rates. With two transfers per cycle of a quadrupled clock, a 64-bit
Bit
A bit is the basic unit of information in computing and telecommunications; it is the amount of information stored by a digital device or other physical system that exists in one of two possible distinct states...
wide DDR3 module may achieve a transfer rate of up to 64 times the memory clock speed in megabyte
Megabyte
The megabyte is a multiple of the unit byte for digital information storage or transmission with two different values depending on context: bytes generally for computer memory; and one million bytes generally for computer storage. The IEEE Standards Board has decided that "Mega will mean 1 000...
s per second (MB/s). With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR3 SDRAM gives a maximum transfer rate of 6400 MB/s. In addition, the DDR3 standard permits chip capacities of up to 8 gigabit
Gigabit
The gigabit is a multiple of the unit bit for digital information or computer storage. The prefix giga is defined in the International System of Units as a multiplier of 109 , and therefore...
s.
Overview
DDR3 memory provides a reduction in power consumption of 30% compared to DDR2DDR2 SDRAM
DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM...
modules due to DDR3's 1.5 V supply voltage, compared to DDR2's 1.8 V or DDR's 2.5 V. The 1.5 V supply voltage works well with the 90 nanometer
90 nanometer
The 90 nm process refers to the level of CMOS process technology that was reached in the 2002–2003 timeframe, by most leading semiconductor companies, like Intel, AMD, Infineon, Texas Instruments, IBM, and TSMC....
fabrication technology used in the original DDR3 chips. Some manufacturers further propose using "dual-gate" transistors
Multigate device
A multigate device or multiple gate field-effect transistor refers to a MOSFET which incorporates more than one gate into a single device. The multiple gates may be controlled by a single gate electrode, wherein the multiple gate surfaces act electrically as a single gate, or by independent gate...
to reduce leakage
Leakage (electronics)
In electronics, leakage may refer to a gradual loss of energy from a charged capacitor. It is primarily caused by electronic devices attached to the capacitors, such as transistors or diodes, which conduct a small amount of current even when they are turned off...
of current.
According to JEDEC
JEDEC
The JEDEC Solid State Technology Association, formerly known as the Joint Electron Devices Engineering Council , is an independent semiconductor engineering trade organization and standardization body...
the maximum recommended voltage is 1.575 volts and should be considered the absolute maximum when memory stability is the foremost consideration, such as in servers or other mission critical devices. In addition, JEDEC states that memory modules must withstand up to 1.975 volts before incurring permanent damage, although they are not required to function correctly at that level.
Two low voltage DDR3 standards have been introduced by JEDEC. The DDR3L standard operates with a default voltage of 1.35V, using at least 15% less power than standard voltage (1.5V) DDR3. Modules with DDR3L are labeled ’’PC3L’’, and examples include DDR3L‐800, DDR3L‐1066, DDR3L‐1333, and DDR3L‐1600. The DDR3U standard operates with a default voltage of 1.25V, and modules are labelled ’’PC3U’’.
The main benefit of DDR3 comes from the higher bandwidth made possible by DDR3's 8-burst-deep prefetch buffer
Prefetch buffer
A prefetch buffer is a data buffer employed on modern DRAM chips that allows quick and easy access to multiple data words located on a common physical row in the memory....
, in contrast to DDR2's 4-burst-deep or DDR
DDR SDRAM
Double data rate synchronous dynamic random access memory is a class of memory integrated circuits used in computers. DDR SDRAM has been superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which are either forward or backward compatible with DDR SDRAM, meaning that DDR2 or DDR3 memory modules...
's 2-burst-deep prefetch buffer.
DDR3 modules can transfer data at a rate of 800–2133 MT/s using both rising and falling edges
Double data rate
In computing, a computer bus operating with double data rate transfers data on both the rising and falling edges of the clock signal. This is also known as double pumped, dual-pumped, and double transition....
of a 400–1066 MHz I/O clock. Sometimes, a vendor may misleadingly advertise the I/O clock rate by labeling the MT/s as MHz. The MT/s is normally twice that of MHz by double sampling, one on the rising clock edge, and the other, on the falling. In comparison, DDR2's current range of data transfer rates is 400–1066 MT/s using a 200–533 MHz I/O clock, and DDR's range is 200–400 MT/s based on a 100–200 MHz I/O clock. High-performance graphics was an initial driver of such bandwidth requirements, where high bandwidth data transfer between framebuffer
Framebuffer
A framebuffer is a video output device that drives a video display from a memory buffer containing a complete frame of data.The information in the memory buffer typically consists of color values for every pixel on the screen...
s is required.
DDR3 does use the same electric signaling standard as DDR
DDR SDRAM
Double data rate synchronous dynamic random access memory is a class of memory integrated circuits used in computers. DDR SDRAM has been superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which are either forward or backward compatible with DDR SDRAM, meaning that DDR2 or DDR3 memory modules...
and DDR2
DDR2 SDRAM
DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM...
, Stub Series Terminated Logic
Stub Series Terminated Logic
Stub Series Terminated Logic is a group of electrical standards for driving transmission lines commonly used with DRAM based DDR memory IC's and memory modules . Primarily designed for driving the DDR SDRAM modules used in computer memory...
, albeit at different timings and voltages. Specifically DDR3 uses SSTL_15.
DDR3 prototypes were announced in early 2005. Products in the form of motherboards appeared on the market in June 2007 based on Intel
Intel Corporation
Intel Corporation is an American multinational semiconductor chip maker corporation headquartered in Santa Clara, California, United States and the world's largest semiconductor chip maker, based on revenue. It is the inventor of the x86 series of microprocessors, the processors found in most...
's P35 "Bearlake" chipset
Intel P35
The P35 Express is a mainstream desktop computer chipset from Intel released in June 2007, although motherboards featuring the chipset were available a month earlier. The P35 Express chipset supports Intel's LGA 775 socket and Core 2 Duo and Quad processors, and is also known to support...
with DIMMs at bandwidths up to DDR3-1600 (PC3-12800). The Intel Core i7, released in November 2008, connects directly to memory rather than via a chipset. The Core i7 supports only DDR3. AMD
Advanced Micro Devices
Advanced Micro Devices, Inc. or AMD is an American multinational semiconductor company based in Sunnyvale, California, that develops computer processors and related technologies for commercial and consumer markets...
's first socket AM3
Socket AM3
Socket AM3 is a CPU socket for AMD processors. AM3 was launched as the successor to Socket AM2+ on February 9, 2009, alongside the initial grouping of Phenom II processors designed for it...
Phenom II
Phenom II
Phenom II is a family of AMD's multi-core 45 nm processors using the AMD K10 microarchitecture, succeeding the original Phenom. Advanced Micro Devices released the Socket AM2+ version of Phenom II in December 2008, while Socket AM3 versions with DDR3 support, along with an initial batch of...
X4 processors, released in February 2009, were their first to support DDR3.
DDR3 DIMM
DIMM
A DIMM or dual in-line memory module, comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers...
s have 240 pins and are electrically incompatible with DDR2. The two are prevented from being accidentally interchanged by different key notch positions on the DIMMs. DDR3 SO-DIMM
SO-DIMM
A SO-DIMM, or small outline dual in-line memory module, is a type of computer memory built using integrated circuits.SO-DIMMs are a smaller alternative to a DIMM, being roughly half the size of regular DIMMs...
s have 204 pins.
GDDR3
GDDR3
Graphics Double Data Rate 3 is a graphics card-specific memory technology, designed by ATI Technologies with the collaboration of JEDEC.It has much the same technological base as DDR2, but the power and heat dispersal requirements have been reduced somewhat, allowing for higher performance memory...
memory, sometimes incorrectly referred to as "DDR3" due to its similar name, is an entirely different technology, as it is designed for use in graphics cards and technologically based on DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM...
.
Latencies
While the typical latenciesSDRAM latency
SDRAM latency refers to delays in transmitting data between the CPU and SDRAM. SDRAM latency is often measured in memory bus clock cycles. However, the CPU operates faster than the memory, so it must wait while the proper segment of memory is located and read, before the data can be sent back...
for a JEDEC DDR2 device were 5-5-5-15, some standard latencies for JEDEC DDR3 devices include 7-7-7-20 for DDR3-1066 and 8-8-8-24 for DDR3-1333.
DDR3 latencies are numerically higher because the I/O bus clock cycles by which they are measured are shorter; the actual time interval is similar to DDR2 latencies (around 10 ns). There is some improvement because DDR3 generally uses more recent manufacturing processes, but this is not directly caused by the change to DDR3.
As with earlier memory generations, faster DDR3 memory became available after the release of the initial versions. DDR3-2000 memory with 9-9-9-28 latency (9 ns) was available in time to coincide with the Intel Core i7 release. CAS latency
CAS Latency
Column Address Strobe latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular memory column on a RAM memory module, and the moment the data from given array location is available on the module's output pins...
of 9 at 1000 MHz (DDR3-2000) is 9 ns, while CAS latency of 7 at 667 MHz (DDR3-1333) is 10.5 ns.
(CAS / Frequency (MHz)) × 1000 = X ns
Example:
(7 / 667) × 1000 = 10.4948 ns
Extensions
Intel Corporation officially introduced the eXtreme Memory Profile (XMP) Specification on March 23, 2007 to enable enthusiast performance extensions to the traditional JEDEC SPDSerial Presence Detect
Serial presence detect refers to a standardized way to automatically access information about a computer memory module. Earlier 72-pin SIMMs included 5 pins which provided 5 bits of parallel presence detect data, but the 168-pin DIMM standard changed to a serial presence detect to encode much...
specifications for DDR3 SDRAM.
JEDEC standard modules
| Standard name |
Memory clock (MHz) |
Cycle time (ns) |
I/O bus clock (MHz) |
Data rate (MT/s) |
Module name |
Peak transfer rate (MB/s) |
Timings (CL-tRCD-tRP) |
CAS latency (ns) |
|---|---|---|---|---|---|---|---|---|
| DDR3-800D DDR3-800E |
100 | 10 | 400 | 800 | PC3-6400 | 6400 | 5-5-5 6-6-6 |
15 |
| DDR3-1066E DDR3-1066F DDR3-1066G |
133⅓ | 533⅓ | 1066⅔ | PC3-8500 | 8533⅓ | 6-6-6 7-7-7 8-8-8 |
15 |
|
| DDR3-1333F* DDR3-1333G DDR3-1333H DDR3-1333J* |
166⅔ | 6 | 666⅔ | 1333⅓ | PC3-10600 | 10666⅔ | 7-7-7 8-8-8 9-9-9 10-10-10 |
12 15 |
| DDR3-1600G* DDR3-1600H DDR3-1600J DDR3-1600K |
200 | 5 | 800 | 1600 | PC3-12800 | 12800 | 8-8-8 9-9-9 10-10-10 11-11-11 |
10 |
| DDR3-1866J* DDR3-1866K DDR3-1866L DDR3-1866M* |
233⅓ | 933⅓ | 1866⅔ | PC3-14900 | 14933⅓ | 10-10-10 11-11-11 12-12-12 13-13-13 |
|
|
| DDR3-2133K* DDR3-2133L DDR3-2133M DDR3-2133N* |
266⅔ | 1066⅔ | 2133⅓ | PC3-17000 | 17066⅔ | 11-11-11 12-12-12 13-13-13 14-14-14 |
|
CL
CAS Latency
Column Address Strobe latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular memory column on a RAM memory module, and the moment the data from given array location is available on the module's output pins...
- Clock cycles between sending a column address to the memory and the beginning of the data in response
tRCD - Clock cycles between row activate and reads/writes
tRP - Clock cycles between row precharge and activate
Fractional frequencies are normally rounded down, but rounding up to -667 is common due to the exact number being -666⅔ and rounding to the nearest whole number. Some manufacturers also round to a certain precision or round up instead, as such PC3-10666 memory could also be listed as PC3-10600 or PC3-10700 despite operating at the same frequency.
Note: All above listed are specified by JEDEC
JEDEC
The JEDEC Solid State Technology Association, formerly known as the Joint Electron Devices Engineering Council , is an independent semiconductor engineering trade organization and standardization body...
as JESD79-3D. All RAM data rates in-between or above these listed specifications are not standardized by JEDEC—often they are simply manufacturer optimizations using higher-tolerance or overvolted chips. Of these non-standard specifications, the highest reported speed reached was equivalent to DDR3-2544 as of May 2010.
DDR3-xxx denotes data transfer rate, and describes raw DDR chips, whereas PC3-xxxx denotes theoretical bandwidth (with the last two digits truncated), and is used to describe assembled DIMMs. Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR3 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.
In addition to bandwidth and capacity variants, modules can
- Optionally implement ECC, which is an extra data byte lane used for correcting minor errors and detecting major errors for better reliability. Modules with ECC are identified by an additional ECC or E in their designation. For example: "PC3-6400 ECC", or PC3-8500E.
- Be "registered"Registered memoryRegistered memory modules have a register between the DRAM modules and the system's memory controller. They place less electrical load on the memory controller and allow single systems to remain stable with more memory modules than they would have otherwise...
, which improves signal integrity (and hence potentially clock rates and physical slot capacity) by electrically buffering the signals with a registerHardware registerIn digital electronics, especially computing, a hardware register stores bits of information, in a way that all the bits can be written to or read out simultaneously.The hardware registers inside a central processing unit are called processor registers....
, at a cost of an extra clock of increased latency. Those modules are identified by an additional R in their designation, whereas non-registered (a.k.a. "unbufferedUnbuffered memoryUnbuffered memory is RAM where there is no hardware register between the memory controller and the RAM chips. Unbuffered memory is the opposite of registered memory. Registered memory is more stable, one clock cycle slower, and more expensive than unbuffered memory...
") RAM may be identified by an additional U in the designation. PC3-6400R is a registered PC3-6400 module, PC3-6400R ECC is the same module but with additional ECC. - Be fully bufferedFully Buffered DIMMFully Buffered DIMM is a memory technology which can be used to increase reliability and density of memory systems. Conventionally, data lines from the memory controller have to be connected to data lines in every DRAM module. As memory width, as well as access speed, increases, the signal...
modules, which are designated by F or FB and do not have the same notch position as other classes. Fully buffered modules cannot be used with motherboards that are made for registered modules, and the different notch position physically prevents their insertion.
Feature summary
DDR3 SDRAM components- Introduction of asynchronous RESET pin
- Support of system-level flight-time compensation
- On-DIMMDIMMA DIMM or dual in-line memory module, comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers...
mirror-friendly DRAM pinout - Introduction of CWL (CAS write latency) per clock bin
- On-die I/O calibration engine
- READ and WRITE calibration
DDR3 modules
- Fly-by command/address/control bus with on-DIMM termination
- High-precision calibration resistors
- Are not backwards compatibleBackward compatibilityIn the context of telecommunications and computing, a device or technology is said to be backward or downward compatible if it can work with input generated by an older device...
—DDR3 modules do not fit into DDR2 sockets; forcing them can damage the DIMM and/or the motherboard
Technological advantages compared to DDR2
- Higher bandwidth performance, up to 2133 MT/s standardized
- Slightly improved latencies as measured in nanoseconds
- Higher performance at low power (longer battery life in laptops)
- Enhanced low-power features
Development and market penetration
In May 2005, Desi Rhoden, chairman of the JEDECJEDEC
The JEDEC Solid State Technology Association, formerly known as the Joint Electron Devices Engineering Council , is an independent semiconductor engineering trade organization and standardization body...
Committee responsible for creating the DDR3 standard, stated that DDR3 had been under development for "about 3 years". DDR3 was launched in 2007, however sales were not expected to overtake DDR2 until the end of 2009, or possibly early 2010, according to Intel strategist Carlos Weissenberg, speaking during the early part of their roll-out in August 2008 (the same timescale for market penetration had been stated by market intelligence
Marketing Intelligence
Marketing Intelligence is the information relevant to a company’s markets, gathered and analyzed specifically for the purpose of accurate and confident decision-making in determining market opportunity, market penetration strategy, and market development metrics. Marketing intelligence is...
company DRAMeXchange over a year earlier in April 2007. and by Desi Rhoden in 2005) The primary driving force behind the increased usage of DDR3 has been new Core i7 processors from Intel and Phenom II
Phenom II
Phenom II is a family of AMD's multi-core 45 nm processors using the AMD K10 microarchitecture, succeeding the original Phenom. Advanced Micro Devices released the Socket AM2+ version of Phenom II in December 2008, while Socket AM3 versions with DDR3 support, along with an initial batch of...
processors from AMD, both of which have internal memory controllers: the latter recommends DDR3, the former requires it. IDC
International Data Corporation
International Data Corporation is a market research and analysis firm specializing in information technology, telecommunications and consumer technology. IDC is a subsidiary of International Data Group...
stated in January 2009 that DDR3 sales will account for 29 percent of the total DRAM units sold in 2009, rising to 72% by 2011.
Successor
JEDEC's planned successor to DDR3 is DDR4, whose standard is currently in development. The primary benefits of DDR4 compared to DDR3 include a higher range of clock frequencies and data transfer rates and significantly lower voltageVoltage
Voltage, otherwise known as electrical potential difference or electric tension is the difference in electric potential between two points — or the difference in electric potential energy per unit charge between two points...
. Some manufacturers have already demonstrated DDR4 chips for testing purposes.
See also
- Dual-channel architectureDual-channel architectureMulti-channel architecture is a technology that increases the transfer speed of data between the RAM and the memory controller by adding more channels of communication between them. Theoretically this multiplies the data rate by exactly the number of channels present. Dual-channel memory employs...
- Triple-channel architecture
- List of device bandwidths