Serial Presence Detect
Encyclopedia
Serial presence detect refers to a standardized way to automatically access information about a computer memory module. Earlier 72-pin SIMM
s included 5 pins which provided 5 bits of parallel presence detect (PPD) data, but the 168-pin DIMM
standard changed to a serial presence detect to encode much more information.
When an ordinary modern computer is turned on, it starts by doing a power-on self-test
(POST). Since about the mid-1990s, this process includes automatically configuring the hardware currently present. SPD is a memory hardware feature that makes it possible for the computer to know what memory is present, and what timings to use to access the memory.
Some computers adapt to hardware changes completely automatically. In most cases, there is a special optional procedure for accessing BIOS
parameters, to view and potentially make changes in settings. It may be possible to control how the computer uses the memory SPD data—to choose which settings to use, to selectively modify the memory timings, or possibly to completely over-ride the SPD data (see overclocking
).
standards require certain parameters to be placed in the lower 128 bytes of an EEPROM
located on the memory module. These bytes contain timing parameters, manufacturer, serial number and other useful information about the module. This data allows a device utilizing the memory to automatically determine key parameters of the module. For example, the SPD data on an SDRAM
module might provide information about the CAS latency
, allowing this to be correctly set without user intervention.
The SPD EEPROM is accessed using SMBus, a variant of the I²C
protocol. This reduces the number of communication pins on the module to just two: a clock signal and a data signal. The EEPROM shares ground pins with the RAM, has its own power pin, and has three additional pins (SA0–2) to identify the slot, which are used to assign the EEPROM a unique address in the range 0x50–0x57. Not only can the communication lines be shared among 8 memory modules, the same SMBus is commonly used on motherboards for system health monitoring tasks such as reading power supply voltages, CPU
temperatures, and fan speeds.
(SPD EEPROMs also respond to I²C addresses 0x30–0x37 if they have not been write protected, and an extension uses addresses 0x18–0x1F to access an optional on-chip temperature sensor.)
memory specification. Most values specified are in binary coded decimal form. The most significant nibble can contain values from 10 to 15, and in some cases extends higher. In such cases, the encodings for 1, 2 and 3 are instead used to encode 16, 17 and 18. A most significant nibble of 0 is reserved to represent "undefined".
The SPD ROM defines up to three DRAM timings, for three CAS latencies specified by set bits in byte 18. First comes the highest CAS latency (fastest clock), then two lower CAS latencies with progressively lower clock speeds.
For cycle time fields (bytes 9, 23, 25 and 49) which are encoded in BCD
, some additional encodings are defined for the tenths digit to represent some common timings exactly:
The memory capacity of a module can be computed from bytes 4, 7 and 8. The module width (byte 8) divided by the number of bits per chip (byte 7) gives the number of chips per rank. That can then be multiplied by the per-chip capacity (byte 4) and the number of ranks of chips on the module (usually 1 or 2, from byte 7).
Enhanced Performance Profiles is an extension of SPD, developed by NVIDIA
and Corsair
, which includes additional information for higher-performance operation of DDR2 SDRAM
, including supply voltages and command timing information not included in the JEDEC SPD spec. The EPP information is stored in the same EEPROM, but in bytes 99-127 which are unused by standard DDR2 SPD.
The parameters are particularly designed to fit the memory controller on the nForce 5
, nForce 6
and nForce 7
chipsets. NVIDIA encourages support for EPP in the BIOS
for its high-end motherboard chipsets. This is intended to provide "one-click overclocking
" to get better performance with minimal effort.
NVIDIA's name for EPP memory that has been qualified for performance and stability is "SLI-ready memory". The term "SLI-ready-memory" has caused some confusion, as it has nothing to do with SLI video
. One can use EPP/SLI memory with a single video card (even a non-NVIDIA card), and one can run a multi-card SLI video setup without EPP/SLI memory.
An extended version, EPP 2.0, supports DDR3 memory as well.
DIMMs. This uses bytes 176–255, which are unallocated by JEDEC, to encode higher-performance memory timings.
The header contains the following data. Most importantly, it contains a "medium timebase" value MTB, as a rational number of nanoseconds (common values are 1/8, 1/12 and 1/16 ns). Many other later timing values are expressed as an integer number of MTB units.
Also included in the header is the number of DIMMS per memory channel that the profile is designed to support; including more DIMMS may not work well.
This is the output of a 512 MB memory module from Micron Technologies, branded for Fujitsu-Siemens Computers, note the "FSC" string.
Memory modules which do not have this information starting at offset 128h will be refused by the BIOS of the system.
on the module. Motherboard BIOS
es read the SPD information to configure the memory controller. There exist several programs that are able to read and modify SPD information on most, but not all motherboard chipsets.
Chipset-independent reading and writing of SPD information is done by accessing the memory's EEPROM directly with eeprom programmer hardware and software.
The method used is to de-assert the /CE line so the internal memory shuts down, allowing the external device to access the SMBus.
Once this is done, a custom Linux build or DOS application can then access the external device; a common use is recovering data from LCD panel memory chips in order to retrofit a generic panel into a proprietary laptop.
s with SPD (more commonly called simply presence detect or PD). Some of this equipment uses non-standard PD coding; IBM
computers and Hewlett-Packard
LaserJet
and other printers in particular. While old computers are rarely found, many old Laserjet printers are in use. Discontinued HP memory modules are officially recommended, but any 72-pin SIMM module within the capacity range supported by the printer and with the correct PD code should work. All printers will work with FPM (Fast Page Mode) memory; it is reported that some, but not all, will work with EDO memory. It is fairly easy to solder wires to the PD pins to make non-HP modules work. HP printers of this type specify that RAM with an access time of or slower to be used; this is likely due to a limitation of the encoding in the PD data. Faster RAM can be used, but the PD encoded data should indicate a speed of .
SIMM
A SIMM, or single in-line memory module, is a type of memory module containing random access memory used in computers from the early 1980s to the late 1990s. It differs from a dual in-line memory module , the most predominant form of memory module today, in that the contacts on a SIMM are redundant...
s included 5 pins which provided 5 bits of parallel presence detect (PPD) data, but the 168-pin DIMM
DIMM
A DIMM or dual in-line memory module, comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers...
standard changed to a serial presence detect to encode much more information.
When an ordinary modern computer is turned on, it starts by doing a power-on self-test
Power-on self-test
Power-On Self-Test refers to routines run immediately after power is applied, by nearly all electronic devices. Perhaps the most widely-known usage pertains to computing devices...
(POST). Since about the mid-1990s, this process includes automatically configuring the hardware currently present. SPD is a memory hardware feature that makes it possible for the computer to know what memory is present, and what timings to use to access the memory.
Some computers adapt to hardware changes completely automatically. In most cases, there is a special optional procedure for accessing BIOS
BIOS
In IBM PC compatible computers, the basic input/output system , also known as the System BIOS or ROM BIOS , is a de facto standard defining a firmware interface....
parameters, to view and potentially make changes in settings. It may be possible to control how the computer uses the memory SPD data—to choose which settings to use, to selectively modify the memory timings, or possibly to completely over-ride the SPD data (see overclocking
Overclocking
Overclocking is the process of operating a computer component at a higher clock rate than it was designed for or was specified by the manufacturer, but some manufacturers purposely underclock their components to improve battery life. Many people just overclock or 'rightclock' their hardware to...
).
Stored information
In order for a memory module to support SPD, the JEDECJEDEC
The JEDEC Solid State Technology Association, formerly known as the Joint Electron Devices Engineering Council , is an independent semiconductor engineering trade organization and standardization body...
standards require certain parameters to be placed in the lower 128 bytes of an EEPROM
EEPROM
EEPROM stands for Electrically Erasable Programmable Read-Only Memory and is a type of non-volatile memory used in computers and other electronic devices to store small amounts of data that must be saved when power is removed, e.g., calibration...
located on the memory module. These bytes contain timing parameters, manufacturer, serial number and other useful information about the module. This data allows a device utilizing the memory to automatically determine key parameters of the module. For example, the SPD data on an SDRAM
SDRAM
Synchronous dynamic random access memory is dynamic random access memory that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs...
module might provide information about the CAS latency
CAS Latency
Column Address Strobe latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular memory column on a RAM memory module, and the moment the data from given array location is available on the module's output pins...
, allowing this to be correctly set without user intervention.
The SPD EEPROM is accessed using SMBus, a variant of the I²C
I²C
I²C is a multi-master serial single-ended computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, cellphone, or other electronic device. Since the mid 1990s, several competitors I²C ("i-squared cee" or "i-two cee"; Inter-Integrated Circuit;...
protocol. This reduces the number of communication pins on the module to just two: a clock signal and a data signal. The EEPROM shares ground pins with the RAM, has its own power pin, and has three additional pins (SA0–2) to identify the slot, which are used to assign the EEPROM a unique address in the range 0x50–0x57. Not only can the communication lines be shared among 8 memory modules, the same SMBus is commonly used on motherboards for system health monitoring tasks such as reading power supply voltages, CPU
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
temperatures, and fan speeds.
(SPD EEPROMs also respond to I²C addresses 0x30–0x37 if they have not been write protected, and an extension uses addresses 0x18–0x1F to access an optional on-chip temperature sensor.)
SDR SDRAM
The first SPD specification was issued by JEDEC and tightened up by Intel as part of its PC100PC100
PC100 is a standard for internal removable computer random access memory, defined by the JEDEC. PC100 refers to Synchronous DRAM operating at a clock frequency of 100 MHz, on a 64-bit-wide bus, at a voltage of 3.3 V. PC100 is available in 168-pin DIMM and 144-pin SO-DIMM form factors...
memory specification. Most values specified are in binary coded decimal form. The most significant nibble can contain values from 10 to 15, and in some cases extends higher. In such cases, the encodings for 1, 2 and 3 are instead used to encode 16, 17 and 18. A most significant nibble of 0 is reserved to represent "undefined".
The SPD ROM defines up to three DRAM timings, for three CAS latencies specified by set bits in byte 18. First comes the highest CAS latency (fastest clock), then two lower CAS latencies with progressively lower clock speeds.
| Byte,d | Byte,x | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | Notes |
|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0x00 | Number of bytes written | Typically 128 | |||||||
| 1 | 0x01 | log2(size of SPD EEPROM) | Typically 8 (256 bytes) | |||||||
| 2 | 0x02 | Basic memory type (4 = SPD SDRAM) | ||||||||
| 3 | 0x03 | Bank 2 row address bits (0–15) | Bank 1 row address bits (1–15) | Bank 2 is 0 if same as bank 1. | ||||||
| 4 | 0x04 | Bank 2 column address bits (0–15) | Bank 1 column address bits (1–15) | Bank 2 is 0 if same as bank 1. | ||||||
| 5 | 0x05 | Number of RAM banks on module (1–255) | Commonly 1 or 2 | |||||||
| 6 | 0x06 | Module data width low byte | Commonly 64, or 72 for ECC DIMMs | |||||||
| 7 | 0x07 | Module data width high byte | Zero unless width ≥ 256 bits | |||||||
| 8 | 0x08 | Interface voltage level of this assembly (not the same as Vcc supply voltage) (0–4) | Decoded by table lookup | |||||||
| 9 | 0x09 | Nanoseconds (0–15) | Tenths of nanoseconds (0.0–0.9) | Clock cycle time at highest CAS latency. | ||||||
| 10 | 0x0a | Nanoseconds (0–15) | Tenths of nanoseconds (0.0–0.9) | SDRAM access time from clock (tAC) | ||||||
| 11 | 0x0b | DIMM configuration type (0–2): non-ECC, parity, ECC | Table lookup | |||||||
| 12 | 0x0c | Self | Refresh period (0–5): 64, 256, 128, 32, 16, 8 kHz | Refresh requirements | ||||||
| 13 | 0x0d | Bank 2 2× | Bank 1 primary SDRAM width (1–127, usually 8) | Width of bank 1 data SDRAM devices. Bank 2 may be same width, or 2× width if bit 7 is set. | ||||||
| 14 | 0x0e | Bank 2 2× | Bank 1 ECC SDRAM width (0–127) | Width of bank 1 ECC/parity SDRAM devices. Bank 2 may be same width, or 2× width if bit 7 is set. | ||||||
| 15 | 0x0f | Clock delay for random column reads | Typically 1 | |||||||
| 16 | 0x10 | Page | — | — | — | 8 | 4 | 2 | 1 | Burst lengths supported (bitmap) |
| 17 | 0x11 | Banks per SDRAM device (1–255) | Typically 2 or 4 | |||||||
| 18 | 0x12 | — | 7 | 6 | 5 | 4 | 3 | 2 | 1 | latencies supported (bitmap) |
| 19 | 0x13 | — | 6 | 5 | 4 | 3 | 2 | 1 | 0 | latencies supported (bitmap) |
| 20 | 0x14 | — | 6 | 5 | 4 | 3 | 2 | 1 | 0 | latencies supported (bitmap) |
| 21 | 0x15 | — | Redundant | Diff clock | Registered data | Buffered data | On-card PLL | Registered Addr | Buffered Addr | Memory module feature bitmap |
| 22 | 0x16 | — | — | Upper Vcc (supply voltage) tolerance | Lower Vcc (supply voltage) tolerance | Write/1 Read Burst | Precharge All | Auto-precharge | Early precharge | Memory chip feature support bitmap |
| 23 | 0x17 | Nanoseconds (4–18) | Tenths of nanoseconds (0.0–0.9) | Clock cycle time at medium CAS latency. | ||||||
| 24 | 0x18 | Nanoseconds (4–18) | Tenths of nanoseconds (0.0–0.9) | Data access time from clock (tAC) | ||||||
| 25 | 0x19 | Nanoseconds (1–63) | 0.25 ns (0–0.75) | Clock cycle time at short CAS latency. | ||||||
| 26 | 0x1a | Nanoseconds (1–63) | 0.25 ns (0–0.75) | Data access time from clock (tAC) | ||||||
| 27 | 0x1b | Nanoseconds (1–255) | Minimum row precharge time (tRP) | |||||||
| 28 | 0x1c | Nanoseconds (1–255) | Minimum row active–row active delay (tRRD) | |||||||
| 29 | 0x1d | Nanoseconds (1–255) | Minimum to delay (tRCD) | |||||||
| 30 | 0x1e | Nanoseconds (1–255) | Minimum active to precharge time (tRAS) | |||||||
| 31 | 0x1f | 512 MiB | 256 MiB | 128 MiB | 64 MiB | 32 MiB | 16 MiB | 8 MiB | 4 MiB | Module bank density (bitmap). Two bits set if different size banks. |
| 32 | 0x20 | Sign (1=neg) | Nanoseconds (0–7) | Tenths of nanoseconds (0.0–0.9) | Address/command setup time from clock | |||||
| 33 | 0x21 | Sign (1=neg) | Nanoseconds (0–7) | Tenths of nanoseconds (0.0–0.9) | Address/command hold time after clock | |||||
| 34 | 0x22 | Sign (1=neg) | Nanoseconds (0–7) | Tenths of nanoseconds (0.0–0.9) | Data input setup time from clock | |||||
| 35 | 0x23 | Sign (1=neg) | Nanoseconds (0–7) | Tenths of nanoseconds (0.0–0.9) | Data input hold time after clock | |||||
| 36–61 | 0x24–0x3d | Reserved | For future standardization | |||||||
| 62 | 0x3e | Major revision (0–9) | Minor revision (0.0–0.9) | SPD revision level, e.g. 1.2 | ||||||
| 63 | 0x3f | Checksum | Sum of bytes 0–62, not negated | |||||||
| 64–71 | 0x40–47 | Manufacturer JEDEC ID | Stored little-endian, trailing zero-pad. | |||||||
| 72 | 0x48 | Module manufacturing location | Vendor-specific code | |||||||
| 73–90 | 0x49–0x5a | Module part number | ASCII, space-padded | |||||||
| 91–92 | 0x5b–0x5c | Module revision code | Vendor-specific code | |||||||
| 93 | 0x5d | Tens of years (00–90) | years (0–9) | Manufacturing date (YYWW) | ||||||
| 94 | 0x5e | Tens of weeks (00–50) | weeks (0–9) | |||||||
| 95–98 | 0x5f–0x62 | Module serial number | Vendor-specific code | |||||||
| 99–125 | 0x63–0x7f | Manufacturer-specific data | Could be enhanced performance profile | |||||||
| 126 | 0x7e | 0x66 for 66 MHz, 0x64 for 100 MHz | Intel frequency support | |||||||
| 127 | 0x7f | CLK0 | CLK1 | CLK3 | CLK3 | 90/100°C | CL3 | CL2 | Concurrent AP | Intel feature bitmap |
DDR SDRAM
The DDR DIMM SPD format is an extension of the SDR SDRAM one. Mostly, parameter ranges are rescaled to accommodate higher speeds.| Byte,d | Byte,x | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | Notes |
|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0x00 | Number of bytes written | Typically 128 | |||||||
| 1 | 0x01 | log2(size of SPD EEPROM) | Typically 8 (256 bytes) | |||||||
| 2 | 0x02 | Basic memory type (7 = DDR SDRAM) | ||||||||
| 3 | 0x03 | Bank 2 row address bits (0–15) | Bank 1 row address bits (1–15) | Bank 2 is 0 if same as bank 1. | ||||||
| 4 | 0x04 | Bank 2 column address bits (0–15) | Bank 1 column address bits (1–15) | Bank 2 is 0 if same as bank 1. | ||||||
| 5 | 0x05 | Number of RAM banks on module (1–255) | Commonly 1 or 2 | |||||||
| 6 | 0x06 | Module data width low byte | Commonly 64, or 72 for ECC DIMMs | |||||||
| 7 | 0x07 | Module data width high byte | Zero unless width ≥ 256 bits | |||||||
| 8 | 0x08 | Interface voltage level of this assembly (not the same as Vcc supply voltage) (0–5) | Decoded by table lookup | |||||||
| 9 | 0x09 | Nanoseconds (0–15) | Tenths of nanoseconds (0.0–0.9) | Clock cycle time at highest CAS latency. | ||||||
| 10 | 0x0a | Tenths of nanoseconds (0.0–0.9) | Hundredths of nanoseconds (0.00–0.09) | SDRAM access time from clock (tAC) | ||||||
| 11 | 0x0b | DIMM configuration type (0–2): non-ECC, parity, ECC | Table lookup | |||||||
| 12 | 0x0c | Self | Refresh period (0–5): 64, 256, 128, 32, 16, 8 kHz | Refresh requirements | ||||||
| 13 | 0x0d | Bank 2 2× | Bank 1 primary SDRAM width (1–127) | Width of bank 1 data SDRAM devices. Bank 2 may be same width, or 2× width if bit 7 is set. | ||||||
| 14 | 0x0e | Bank 2 2× | Bank 1 ECC SDRAM width (0–127) | Width of bank 1 ECC/parity SDRAM devices. Bank 2 may be same width, or 2× width if bit 7 is set. | ||||||
| 15 | 0x0f | Clock delay for random column reads | Typically 1 | |||||||
| 16 | 0x10 | Page | — | — | — | 8 | 4 | 2 | 1 | Burst lengths supported (bitmap) |
| 17 | 0x11 | Banks per SDRAM device (1–255) | Typically 4 | |||||||
| 18 | 0x12 | — | 4 | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 | latencies supported (bitmap) |
| 19 | 0x13 | — | 6 | 5 | 4 | 3 | 2 | 1 | 0 | latencies supported (bitmap) |
| 20 | 0x14 | — | 6 | 5 | 4 | 3 | 2 | 1 | 0 | latencies supported (bitmap) |
| 21 | 0x15 | — | x | Diff clock | FET switch external enable | FET switch on-board enable | On-card PLL | Registered | Buffered | Memory module feature bitmap |
| 22 | 0x16 | Fast AP | Concurrent auto precharge | Upper Vcc (supply voltage) tolerance | Lower Vcc (supply voltage) tolerance | — | — | — | Includes weak driver | Memory chip feature bitmap |
| 23 | 0x17 | Nanoseconds (0–15) | Tenths of nanoseconds (0.0–0.9) | Clock cycle time at medium CAS latency. | ||||||
| 24 | 0x18 | Tenths of nanoseconds (0.0–0.9) | Hundredths of nanoseconds (0.00–0.09) | Data access time from clock (tAC) | ||||||
| 25 | 0x19 | Nanoseconds (0–15) | Tenths of nanoseconds (0.0–0.9) | Clock cycle time at short CAS latency. | ||||||
| 26 | 0x1a | Tenths of nanoseconds (0.0–0.9) | Hundredths of nanoseconds (0.00–0.09) | Data access time from clock (tAC) | ||||||
| 27 | 0x1b | Nanoseconds (1–63) | 0.25 ns (0–0.75) | Minimum row precharge time (tRP) | ||||||
| 28 | 0x1c | Nanoseconds (1–63) | 0.25 ns (0–0.75) | Minimum row active–row active delay (tRRD) | ||||||
| 29 | 0x1d | Nanoseconds (1–63) | 0.25 ns (0–0.75) | Minimum to delay (tRCD) | ||||||
| 30 | 0x1e | Nanoseconds (1–255) | Minimum active to precharge time (tRAS) | |||||||
| 31 | 0x1f | 512 MiB | 256 MiB | 128 MiB | 64 MiB | 32 MiB | 16 MiB/ 4 GiB |
8 MiB/ 2 GiB |
4 MiB/ 1 GiB |
Module bank density (bitmap). Two bits set if different size banks. |
| 32 | 0x20 | Tenths of nanoseconds (0.0–0.9) | Hundredths of nanoseconds (0.00–0.09) | Address/command setup time from clock | ||||||
| 33 | 0x21 | Tenths of nanoseconds (0.0–0.9) | Hundredths of nanoseconds (0.00–0.09) | Address/command hold time after clock | ||||||
| 34 | 0x22 | Tenths of nanoseconds (0.0–0.9) | Hundredths of nanoseconds (0.00–0.09) | Data input setup time from clock | ||||||
| 35 | 0x23 | Tenths of nanoseconds (0.0–0.9) | Hundredths of nanoseconds (0.00–0.09) | Data input hold time after clock | ||||||
| 36–40 | 0x24–0x28 | Reserved | Superset information | |||||||
| 41 | 0x29 | Nanoseconds (1–255) | Minimum active to active/refresh time (tRC) | |||||||
| 42 | 0x2a | Nanoseconds (1–255) | Minimum refresh to active/refresh time (tRFC) | |||||||
| 43 | 0x2b | Nanoseconds (1–63) | 0.25 ns (0–0.75) | Maximum clock cycle time (tCK max.) If all-ones, there is no maximum. |
||||||
| 44 | 0x2c | Hundredths of nanoseconds (0.01–2.55) | Maximum skew, DQS to any DQ. (tDQSQ max.) | |||||||
| 45 | 0x2d | Tenths of nanoseconds (0.0–1.2) | Hundredths of nanoseconds (0.00–0.09) | Read data hold skew factor (tQHS) | ||||||
| 46 | 0x2e | Reserved | For future standardization | |||||||
| 47 | 0x2f | — | Height | Height of DIMM module, table lookup | ||||||
| 48–61 | 0x30–0x3d | Reserved | For future standardization | |||||||
| 62 | 0x3e | Major revision (0–9) | Minor revision (0.0–0.9) | SPD revision level, 0.0 or 1.0 | ||||||
| 63 | 0x3f | Checksum | Sum of bytes 0–62, not negated | |||||||
| 64–71 | 0x40–47 | Manufacturer JEDEC ID | Stored little-endian, trailing zero-pad. | |||||||
| 72 | 0x48 | Module manufacturing location | Vendor-specific code | |||||||
| 73–90 | 0x49–0x5a | Module part number | ASCII, space-padded | |||||||
| 91–92 | 0x5b–0x5c | Module revision code | Vendor-specific code | |||||||
| 93 | 0x5d | Tens of years (00–90) | years (0–9) | Manufacturing date (YYWW) | ||||||
| 94 | 0x5e | Tens of weeks (00–50) | weeks (0–9) | |||||||
| 95–98 | 0x5f–0x62 | Module serial number | Vendor-specific code | |||||||
| 99–127 | 0x63–0x7f | Manufacturer-specific data | Could be enhanced performance profile | |||||||
DDR2 SDRAM
The DDR2 SPD standard makes a number of changes, but is roughly similar to the above. One notable deletion is the confusing and little-used support for DIMMs with two ranks of different sizes.For cycle time fields (bytes 9, 23, 25 and 49) which are encoded in BCD
Binary-coded decimal
In computing and electronic systems, binary-coded decimal is a digital encoding method for numbers using decimal notation, with each decimal digit represented by its own binary sequence. In BCD, a numeral is usually represented by four bits which, in general, represent the decimal range 0 through 9...
, some additional encodings are defined for the tenths digit to represent some common timings exactly:
| Hex | Binary | Significance |
|---|---|---|
| A | 1010 | 0.25 (¼) |
| B | 1011 | 0.33̅ (⅓) |
| C | 1100 | 0.66̅ (⅔) |
| D | 1101 | 0.75 (¾) |
| E | 1110 | 0.875 (⅞, nVidia XMP extension) |
| F | 1111 | Reserved, do not use |
| Byte | Byte (hex) | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | Notes |
|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0x00 | Number of bytes written | Typically 128 | |||||||
| 1 | 0x01 | log2(size of SPD EEPROM) | Typically 8 (256 bytes) | |||||||
| 2 | 0x02 | Basic memory type (8 = DDR2 SDRAM) | ||||||||
| 3 | 0x03 | Reserved, zero | Row address bits (1–15) | |||||||
| 4 | 0x04 | Reserved, zero | Column address bits (1–15) | |||||||
| 5 | 0x05 | Vertical height | Stack? | ConC? | Ranks−1 (1–8) | Commonly 0 or 1, meaning 1 or 2 | ||||
| 6 | 0x06 | Module data width | Commonly 64, or 72 for ECC DIMMs | |||||||
| 7 | 0x07 | Reserved, zero | ||||||||
| 8 | 0x08 | Interface voltage level of this assembly (not the same as Vcc supply voltage) (0–5) | Decoded by table lookup. Commonly 5 = SSTL 1.8 V |
|||||||
| 9 | 0x09 | Nanoseconds (0–15) | Tenths of nanoseconds (0.0–0.9) | Clock cycle time at highest CAS latency. | ||||||
| 10 | 0x0a | Tenths of nanoseconds (0.0–0.9) | Hundredths of nanoseconds (0.00–0.09) | SDRAM access time from clock (tAC) | ||||||
| 11 | 0x0b | DIMM configuration type (0–2): non-ECC, parity, ECC | Table lookup | |||||||
| 12 | 0x0c | Self | Refresh period (0–5): 64, 256, 128, 32, 16, 8 kHz | Refresh requirements | ||||||
| 13 | 0x0d | Primary SDRAM width (1–255) | Commonly 8 (module built from ×8 parts) or 16 | |||||||
| 14 | 0x0e | ECC SDRAM width (0–255) | Width of bank ECC/parity SDRAM devices. Commonly 0 or 8. | |||||||
| 15 | 0x0f | Reserved, zero | ||||||||
| 16 | 0x10 | | — | — | — | — | 8 | 4 | — | — | Burst lengths supported (bitmap) |
| 17 | 0x11 | Banks per SDRAM device (1–255) | Typically 4 or 8 | |||||||
| 18 | 0x12 | 7 | 6 | 5 | 4 | 3 | 2 | — | — | latencies supported (bitmap) |
| 19 | 0x13 | Reserved, zero | ||||||||
| 20 | 0x14 | — | — | Mini-UDIMM | Mini-RDIMM | Micro-DIMM | SO-DIMM | UDIMM | RDIMM | DIMM type of this assembly (bitmap) |
| 21 | 0x15 | — | Module is analysis probe | — | FET switch external enable | — | — | — | — | Memory module feature bitmap |
| 22 | 0x16 | — | — | — | — | — | — | — | Includes weak driver | Memory chip feature bitmap |
| 23 | 0x17 | Nanoseconds (0–15) | Tenths of nanoseconds (0.0–0.9) | Clock cycle time at medium CAS latency. | ||||||
| 24 | 0x18 | Tenths of nanoseconds (0.0–0.9) | Hundredths of nanoseconds (0.00–0.09) | Data access time from clock (tAC) | ||||||
| 25 | 0x19 | Nanoseconds (0–15) | Tenths of nanoseconds (0.0–0.9) | Clock cycle time at short CAS latency. | ||||||
| 26 | 0x1a | Tenths of nanoseconds (0.0–0.9) | Hundredths of nanoseconds (0.00–0.09) | Data access time from clock (tAC) | ||||||
| 27 | 0x1b | Nanoseconds (1–63) | 1/4 ns (0–0.75) | Minimum row precharge time (tRP) | ||||||
| 28 | 0x1c | Nanoseconds (1–63) | 1/4 ns (0–0.75) | Minimum row active–row active delay (tRRD) | ||||||
| 29 | 0x1d | Nanoseconds (1–63) | 1/4 ns (0–0.75) | Minimum to delay (tRCD) | ||||||
| 30 | 0x1e | Nanoseconds (1–255) | Minimum active to precharge time (tRAS) | |||||||
| 31 | 0x1f | 512 MiB | 256 MiB | 128 MiB | 16 GiB | 8 GiB | 4 GiB | 2 GiB | 1 GiB | Size of each rank (bitmap). |
| 32 | 0x20 | Tenths of nanoseconds (0.0–1.2) | Hundredths of nanoseconds (0.00–0.09) | Address/command setup time from clock | ||||||
| 33 | 0x21 | Tenths of nanoseconds (0.0–1.2) | Hundredths of nanoseconds (0.00–0.09) | Address/command hold time after clock | ||||||
| 34 | 0x22 | Tenths of nanoseconds (0.0–0.9) | Hundredths of nanoseconds (0.00–0.09) | Data input setup time from strobe | ||||||
| 35 | 0x23 | Tenths of nanoseconds (0.0–0.9) | Hundredths of nanoseconds (0.00–0.09) | Data input hold time after strobe | ||||||
| 36 | 0x24 | Nanoseconds (1–63) | 0.25 ns (0–0.75) | Minimum write recovery time (tWR) | ||||||
| 37 | 0x25 | Nanoseconds (1–63) | 0.25 ns (0–0.75) | Internal write to read command delay (tWTR) | ||||||
| 38 | 0x26 | Nanoseconds (1–63) | 0.25 ns (0–0.75) | Internal read to precharge command delay (tRTP) | ||||||
| 39 | 0x27 | Reserved, zero | Reserved for "memory analysis probe characteristics" | |||||||
| 40 | 0x28 | — | tRC fractional ns (0–5): 0, 0.25, 0.33, 0.5, 0.66, 0.75 |
tRFC fractional ns (0–5): 0, 0.25, 0.33, 0.5, 0.66, 0.75 |
tRFC + 256 ns | Extension of bytes 41 and 42. | ||||
| 41 | 0x29 | Nanoseconds (1–255) | Minimum active to active/refresh time (tRC) | |||||||
| 42 | 0x2a | Nanoseconds (1–255) | Minimum refresh to active/refresh time (tRFC) | |||||||
| 43 | 0x2b | Nanoseconds (0–15) | Tenths of nanoseconds (0.0–0.9) | Maximum clock cycle time (tCK max) | ||||||
| 44 | 0x2c | Hundredths of nanoseconds (0.01–2.55) | Maximum skew, DQS to any DQ. (tDQSQ max) | |||||||
| 45 | 0x2d | Tenths of nanoseconds (0.0–1.2) | Hundredths of nanoseconds (0.00–0.09) | Read data hold skew factor (tQHS) | ||||||
| 46 | 0x2e | Microseconds (1–255) | PLL relock time | |||||||
| 47–61 | 0x2f–0x3d | Reserved | For future standardization. | |||||||
| 62 | 0x3e | Major revision (0–9) | Minor revision (0.0–0.9) | SPD revision level, usually 1.0 | ||||||
| 63 | 0x3f | Checksum | Sum of bytes 0–62, not negated | |||||||
| 64–71 | 0x40–47 | Manufacturer JEDEC ID | Stored little-endian, trailing zero-pad. | |||||||
| 72 | 0x48 | Module manufacturing location | Vendor-specific code | |||||||
| 73–90 | 0x49–0x5a | Module part number | ASCII, space-padded (limited to ,A-Z,a-z,0-9,space) | |||||||
| 91–92 | 0x5b–0x5c | Module revision code | Vendor-specific code | |||||||
| 93 | 0x5d | Years since 2000 (0–255) | Manufacturing date (YYWW) | |||||||
| 94 | 0x5e | Weeks (1–52) | ||||||||
| 95–98 | 0x5f–0x62 | Module serial number | Vendor-specific code | |||||||
| 99–127 | 0x63–0x7f | Manufacturer-specific data | Could be enhanced performance profile | |||||||
DDR3 SDRAM
The DDR3 SDRAM standard significantly overhauls and simplifies the SPD contents layout. Instead of a number of BCD-encoded nanosecond fields, some "timebase" units are specified to high precision, and various timing parameters are encoded as multiples of that base unit. Further, the practice of specifying different time values depending on the CAS latency has been dropped; now there are just a single set of timing parameters.| Byte | b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 | Notes | |
|---|---|---|---|---|---|---|---|---|---|---|
| 0 | 0x00 | CRC exclude 117–125 | SPD bytes total (undef/256) | SPD bytes used (undef/128/176/256) | Bit 7 indicates serial number excluded from CRC | |||||
| 1 | 0x01 | SPD major revision | SPD minor revision | Typically 1.0 | ||||||
| 2 | 0x02 | Basic memory type (11 = DDR3 SDRAM) | Type of RAM chips | |||||||
| 3 | 0x03 | Reserved, zero | Module type | Type of module, e.g. 2 = Unbuffered DIMM, 3 = SO-DIMM | ||||||
| 4 | 0x04 | — | Bank address bits−3 | log2(bits per chip)−28 | Zero means 8 banks, 256 Mibit. | |||||
| 5 | 0x05 | — | Row address bits−12 | Column address bits−9 | ||||||
| 6 | 0x06 | reserved | 1.2x V | 1.35 V | NOT 1.5 V | Modules voltages supported. 1.5V is default. | ||||
| 7 | 0x07 | — | log2(ranks) | log2(I/O bits/chip)−2 | Module organization | |||||
| 8 | 0x08 | — | ECC bits (001=8) | log2(data bits)−3 | 0x03 for 64-bit, non-ECC DIMM. | |||||
| 9 | 0x09 | FTP dividend (1–15) | FTP divisor (1–15) | Fine Time Base = dividend/divisor ps. | ||||||
| 10 | 0x0a | Medium time base dividend (1–255) | MTB = dividend/divisor ns, commonly 1/8 | |||||||
| 11 | 0x0b | Medium time base divisor (1–255) | ||||||||
| 12 | 0x0c | Minimum cycle time tCKmin | In multiples of MTB | |||||||
| 13 | 0x0d | reserved | ||||||||
| 14 | 0x0e | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | CAS latencies supported (bitmap) |
| 15 | 0x0f | — | 18 | 17 | 16 | 15 | 14 | 13 | 12 | |
| 16 | 0x10 | Minimum CAS latency time tAAmin | In multiples of MTB, e.g. 80/8 ns. | |||||||
| 17 | 0x11 | Minimum write recovery time tWRmin | In multiples of MTB, e.g. 120/8 ns. | |||||||
| 18 | 0x12 | Minimum RAS to CAS delay time tRCDmin | In multiples of MTB, e.g. 100/8 ns. | |||||||
| 19 | 0x13 | Minimum row to row active delay time tRRDmin | In multiples of MTB, e.g. 60/8 ns. | |||||||
| 20 | 0x14 | Minimum row precharge time tRPmin | In multiples of MTB, e.g. 100/8 ns. | |||||||
| 21 | 0x15 | tRCmin, bits 11:8 | tRASmin, bits 11:8 | Upper 4 bits of bytes 23 and 22 | ||||||
| 22 | 0x16 | Minimum active to time tRASmin, bits 7:0 | In multiples of MTB, e.g. 280/8 ns. | |||||||
| 23 | 0x17 | Minimum active to active/refresh tRCmin, bits 7:0 | In multiples of MTB, e.g. 396/8 ns. | |||||||
| 24 | 0x18 | Minimum refresh recovery delay tRFCmin, bits 7:0 | In multiples of MTB, e.g. 1280/8 ns. | |||||||
| 25 | 0x19 | Minimum refresh recovery delay tRFCmin, bits 15:8 | ||||||||
| 26 | 0x1a | Minimum internal write to read delay tWTRmin | In multiples of MTB, e.g. 60/8 ns. | |||||||
| 27 | 0x1b | Minimum internal read to precharge delay tRTPmin | In multiples of MTB, e.g. 60/8 ns. | |||||||
| 28 | 0x1c | reserved | tFAWmin, bits 11:8 | In multiples of MTB, e.g. 240/8 ns. | ||||||
| 29 | 0x1d | Minimum four activate window delay tFAWmin, bits 7:0 | ||||||||
| 30 | 0x1e | DLL-off | — | — | — | — | — | RZQ/7 | RZQ/6 | SDRAM optional features support bitmap |
| 31 | 0x1f | PASR | — | — | — | ODTS | ASR | ETR 1× | ETR (95°C) | SDRAM thermal and refresh options |
| 32 | 0x20 | Present | Accuracy (TBD; currently 0 = undefined) | DIMM thermal sensor present? | ||||||
| 33 | 0x21 | Nonstd. | Nonstandard device type | Nonstandard SDRAM device type (e.g. stacked die) | ||||||
| 34–59 | 0x22–0x3b | Reserved | For future standardization. | |||||||
| 60 | 0x3c | — | Module height, ceil(mm)−15 | Module nominal height (31 = Height > 45 mm) | ||||||
| 61 | 0x3d | Back thickness | Front thickness | Module thickness, value=ceil(mm)−1 | ||||||
| 62 | 0x3e | Design | Revision | JEDEC design number | JEDEC reference design used (11111=none) | |||||
| 63–116 | 0x3f–0x74 | Module-specific section | Differs between registered/unbuffered | |||||||
| 117 | 0x75 | Module manufacturer ID, lsbyte | Assigned by JEP-106 | |||||||
| 118 | 0x76 | Module manufacturer ID, msbyte | ||||||||
| 119 | 0x77 | Module manufacturing location | Vendor-specific code | |||||||
| 120 | 0x78 | Decades | Years | Manufacturing year (BCD) | ||||||
| 121 | 0x79 | Tens of weeks | weeks | Manufacturing week (BCD) | ||||||
| 122–125 | 0x7a–0x7d | Module serial number | Vendor-specific code | |||||||
| 126–127 | 0x7e–0x7f | SPD CRC-16 | Includes bytes 0–116 or 0–125; see byte 0 bit 7 | |||||||
| 128–145 | 0x80–0x91 | Module part number | ASCII subset, space-padded | |||||||
| 146–147 | 0x92–0x93 | Module revision code | Vendor-defined | |||||||
| 148–149 | 0x94–0x95 | DRAM manufacturer ID | As distinct from module manufacturer | |||||||
| 150–175 | 0x96–0xAF | Manufacturer-specific data | ||||||||
The memory capacity of a module can be computed from bytes 4, 7 and 8. The module width (byte 8) divided by the number of bits per chip (byte 7) gives the number of chips per rank. That can then be multiplied by the per-chip capacity (byte 4) and the number of ranks of chips on the module (usually 1 or 2, from byte 7).
Extensions
The JEDEC standard only specifies some of the SPD bytes. The truly critical data fits into the first 64 bytes, while some of the remainder is earmarked for manufacturer identification. However, a 256-byte EEPROM is generally provided. A number of uses have been made of the remaining space.Enhanced Performance Profiles (EPP)
Memory generally comes with conservative timing recommendations in the SPD ROM, to ensure basic functionality on all systems. Enthusiasts often spend considerable time manually adjusting the memory timings for higher speed.Enhanced Performance Profiles is an extension of SPD, developed by NVIDIA
NVIDIA
Nvidia is an American global technology company based in Santa Clara, California. Nvidia is best known for its graphics processors . Nvidia and chief rival AMD Graphics Techonologies have dominated the high performance GPU market, pushing other manufacturers to smaller, niche roles...
and Corsair
Corsair
Corsairs were privateers, authorized to conduct raids on shipping of a nation at war with France, on behalf of the French Crown. Seized vessels and cargo were sold at auction, with the corsair captain entitled to a portion of the proceeds...
, which includes additional information for higher-performance operation of DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It supersedes the original DDR SDRAM specification and has itself been superseded by DDR3 SDRAM...
, including supply voltages and command timing information not included in the JEDEC SPD spec. The EPP information is stored in the same EEPROM, but in bytes 99-127 which are unused by standard DDR2 SPD.
| Bytes | Size | Full profiles | Abbreviated profiles |
|---|---|---|---|
| 99–103 | 5 | EPP header | |
| 104–109 | 6 | Profile FP1 | Profile AP1 |
| 110–115 | 6 | Profile AP2 | |
| 116–121 | 6 | Profile FP2 | Profile AP3 |
| 122–127 | 6 | Profile AP4 | |
The parameters are particularly designed to fit the memory controller on the nForce 5
NForce 500
The nForce 500 is a motherboard chipset series and the successor to the nForce4 series. It was revealed by NVIDIA on 2006-03-07 and released on 2006-05-23...
, nForce 6
NForce 600
The nForce 600 chipset was released in the first half of November 2006, coinciding with the GeForce 8 series launch on November 8, 2006. The nForce 600 supports Intel's LGA 775 socket and AMD's Quad FX platform and replaces the nForce 500 series....
and nForce 7
NForce 700
The nForce 700 is a chipset series designed by Nvidia first released in December 2007. The series supports both Intel Core 2 and AMD Phenom processors, and replaces the nForce 600 series chipsets...
chipsets. NVIDIA encourages support for EPP in the BIOS
BIOS
In IBM PC compatible computers, the basic input/output system , also known as the System BIOS or ROM BIOS , is a de facto standard defining a firmware interface....
for its high-end motherboard chipsets. This is intended to provide "one-click overclocking
Overclocking
Overclocking is the process of operating a computer component at a higher clock rate than it was designed for or was specified by the manufacturer, but some manufacturers purposely underclock their components to improve battery life. Many people just overclock or 'rightclock' their hardware to...
" to get better performance with minimal effort.
NVIDIA's name for EPP memory that has been qualified for performance and stability is "SLI-ready memory". The term "SLI-ready-memory" has caused some confusion, as it has nothing to do with SLI video
Scalable Link Interface
Scalable Link Interface is a brand name for a multi-GPU solution developed by NVIDIA for linking two or more video cards together to produce a single output...
. One can use EPP/SLI memory with a single video card (even a non-NVIDIA card), and one can run a multi-card SLI video setup without EPP/SLI memory.
An extended version, EPP 2.0, supports DDR3 memory as well.
Extreme Memory Profile (XMP)
A similar, Intel-developed JEDEC SPD extension for DDR3 SDRAMDDR3 SDRAM
In computing, DDR3 SDRAM, an abbreviation for double data rate type three synchronous dynamic random access memory, is a modern kind of dynamic random access memory with a high bandwidth interface. It is one of several variants of DRAM and associated interface techniques used since the early 1970s...
DIMMs. This uses bytes 176–255, which are unallocated by JEDEC, to encode higher-performance memory timings.
| Bytes | Size | Use |
|---|---|---|
| 176–184 | 10 | XMP header |
| 185–219 | 33 | XMP profile 1 ("enthusiast" settings) |
| 220–254 | 36 | XMP profile 2 ("extreme" settings) |
The header contains the following data. Most importantly, it contains a "medium timebase" value MTB, as a rational number of nanoseconds (common values are 1/8, 1/12 and 1/16 ns). Many other later timing values are expressed as an integer number of MTB units.
Also included in the header is the number of DIMMS per memory channel that the profile is designed to support; including more DIMMS may not work well.
| Byte | Bits | Use |
|---|---|---|
| 176 | 7:0 | XMP magic number Magic number (programming) In computer programming, the term magic number has multiple meanings. It could refer to one or more of the following:* A constant numerical or text value used to identify a file format or protocol; for files, see List of file signatures... byte 1 0x0C |
| 177 | 7:0 | XMP magic number byte 2 0x4A |
| 178 | 0 | Profile 1 enabled (if 0, disabled) |
| 1 | Profile 2 enabled | |
| 3:2 | Profile 1 DIMMS per channel (1–4 encoded as 0–3) | |
| 5:4 | Profile 2 DIMMS per channel | |
| 7:6 | Reserved, must be zero | |
| 179 | 3:0 | XMP minor version number (x.0 or x.1) |
| 7:4 | XMP major version number (0.x or 1.x) | |
| 180 | 7:0 | Medium timebase dividend for profile 1 |
| 181 | 7:0 | Medium timebase divisor for profile 1 (MTB = dividend/divisor ns) |
| 182 | 7:0 | Medium timebase dividend for profile 2 (e.g. 8) |
| 183 | 7:0 | Medium timebase divisor for profile 2 (e.g. 1, giving MTB = 1/8 ns) |
| 184 | 7:0 | Reserved, must be zero |
| Byte 1 | Byte 2 | Bits | Use |
|---|---|---|---|
| 185 | 220 | 4:0 | Module Vdd voltage fraction (x.00–x.95 encoded as 0–19) |
| 6:5 | Module Vdd voltage units (0–2) | ||
| 7 | Reserved, must be zero | ||
| 186 | 221 | 7:0 | Minimum SDRAM clock period tCKmin (MTB units) |
| 187 | 222 | 7:0 | Minimum CAS latency time tAAmin (MTB units) |
| 188 | 223 | 7:0 | CAS latencies supported (bitmap, 4–11 encoded as bits 0–7) |
| 189 | 224 | 6:0 | CAS latencies supported (bitmap, 12–18 encoded as bits 0–6) |
| 7 | Reserved, must be zero | ||
| 190 | 225 | 7:0 | Minimum CAS write latency time tCWLmin (MTB units) |
| 191 | 226 | 7:0 | Minimum row precharge delay time tRPmin (MTB units) |
| 192 | 227 | 7:0 | Minimum RAS to CAS delay time tRCDmin (MTB units) |
| 193 | 228 | 7:0 | Minimum write recovery time tWRmin (MTB units) |
| 194 | 229 | 3:0 | tRASmin upper nibble Nibble In computing, a nibble is a four-bit aggregation, or half an octet... (bits 11:8) |
| 7:4 | tRCmin upper nibble (bits 11:8) | ||
| 195 | 230 | 7:0 | Minimum active to precharge delay time tRASmin bits 7:0 (MTB units) |
| 196 | 231 | 7:0 | Minimum active to active/refresh delay time tRCmin bits 7:0 (MTB units) |
| 197 | 232 | 7:0 | Maximum average refresh interval tREFI lsbyte (MTB units) |
| 198 | 233 | 7:0 | Maximum average refresh interval tREFI msbyte (MTB units) |
| 199 | 234 | 7:0 | Minimum refresh recovery delay time tRFCmin lsbyte (MTB units) |
| 200 | 235 | 7:0 | Minimum refresh recovery delay time tRFCmin msbyte (MTB units) |
| 201 | 236 | 7:0 | Minimum internal read to precharge command delay time tRTPmin (MTB units) |
| 202 | 237 | 7:0 | Minimum row active to row active delay time tRRDmin (MTB units) |
| 203 | 238 | 3:0 | tFAWmin upper nibble (bits 11:8) |
| 7:4 | Reserved, must be zero | ||
| 204 | 239 | 7:0 | Minimum four activate window delay time tFAWmin bits 7:0 (MTB units) |
| 205 | 240 | 7:0 | Minimum internal write to read command delay time tWTRmin (MTB units) |
| 206 | 241 | 2:0 | Write to read command turnaround time adjustment (0–7 clock cycles) |
| 3 | Write to read command turnaround adjustment sign (0=pull-in, 1=push-out) | ||
| 6:4 | Read to write command turnaround time adjustment (0–7 clock cycles) | ||
| 7 | Read to write command turnaround adjustment sign (0=pull-in, 1=push-out) | ||
| 207 | 242 | 2:0 | Back-to-back command turnaround time adjustment (0–7 clock cycles) |
| 3 | Back-to-back turnaround adjustment sign (0=pull-in, 1=push-out) | ||
| 7:4 | Reserved, must be zero | ||
| 208 | 243 | 7:0 | System CMD rate mode. 0=JTAG default, otherwise in peculiar units of MTB × tCK/ns. E.g. if MTB is 1/8 ns, then this is in units of 1/8 clock cycle. |
| 209 | 244 | 7:0 | SDRAM auto self refresh performance. Standard version 1.1 says documentation is TBD. |
| 210–218 | 245–253 | 7:0 | Reserved, must be zero |
| 219 | 254 | 7:0 | Reserved, vendor-specific personality code. |
Vendor-specific memory
A very common (mis-)use is the writing of information to certain memory regions in order to bind vendor-specific memory modules to a specific system. One vendor known to do this is Fujitsu-Siemens Computers. Adding different memory module to the system usually results in a refusal or other counter-measures (like pressing F1 on every boot).
02 0E 00 01-00 00 00 EF-02 03 19 4D-BC 47 C3 46 ...........M.G.F
53 43 00 04-EF 4F 8D 1F-00 01 70 00-01 03 C1 CF SC...O....p.....
This is the output of a 512 MB memory module from Micron Technologies, branded for Fujitsu-Siemens Computers, note the "FSC" string.
Memory modules which do not have this information starting at offset 128h will be refused by the BIOS of the system.
Reading and writing SPD information
Memory module manufacturers write the SPD information to the EEPROMEEPROM
EEPROM stands for Electrically Erasable Programmable Read-Only Memory and is a type of non-volatile memory used in computers and other electronic devices to store small amounts of data that must be saved when power is removed, e.g., calibration...
on the module. Motherboard BIOS
BIOS
In IBM PC compatible computers, the basic input/output system , also known as the System BIOS or ROM BIOS , is a de facto standard defining a firmware interface....
es read the SPD information to configure the memory controller. There exist several programs that are able to read and modify SPD information on most, but not all motherboard chipsets.
- dmidecode program that can decode information about memory (and other things) and runs on LinuxLinuxLinux is a Unix-like computer operating system assembled under the model of free and open source software development and distribution. The defining component of any Linux system is the Linux kernel, an operating system kernel first released October 5, 1991 by Linus Torvalds...
, FreeBSDFreeBSDFreeBSD is a free Unix-like operating system descended from AT&T UNIX via BSD UNIX. Although for legal reasons FreeBSD cannot be called “UNIX”, as the direct descendant of BSD UNIX , FreeBSD’s internals and system APIs are UNIX-compliant...
, NetBSDNetBSDNetBSD is a freely available open source version of the Berkeley Software Distribution Unix operating system. It was the second open source BSD descendant to be formally released, after 386BSD, and continues to be actively developed. The NetBSD project is primarily focused on high quality design,...
, OpenBSDOpenBSDOpenBSD is a Unix-like computer operating system descended from Berkeley Software Distribution , a Unix derivative developed at the University of California, Berkeley. It was forked from NetBSD by project leader Theo de Raadt in late 1995...
, BeOSBeOSBeOS is an operating system for personal computers which began development by Be Inc. in 1991. It was first written to run on BeBox hardware. BeOS was optimized for digital media work and was written to take advantage of modern hardware facilities such as symmetric multiprocessing by utilizing...
, CygwinCygwinCygwin is a Unix-like environment and command-line interface for Microsoft Windows. Cygwin provides native integration of Windows-based applications, data, and other system resources with applications, software tools, and data of the Unix-like environment...
and Solaris. dmidecode does not access SPD information directly; it reports the BIOS data about the memory. This information may be limited or incorrect.
- On LinuxLinuxLinux is a Unix-like computer operating system assembled under the model of free and open source software development and distribution. The defining component of any Linux system is the Linux kernel, an operating system kernel first released October 5, 1991 by Linus Torvalds...
systems, the user spaceUser spaceA conventional computer operating system usually segregates virtual memory into kernel space and user space. Kernel space is strictly reserved for running the kernel, kernel extensions, and most device drivers...
program decode-dimms provided with i2c-tools decodes and prints information on any memory with SPD information in the computer. It requires SMBus controller support in the kernel, the EEPROM kernel driver, and also that the SPD EEPROMs are connected to the SMBus. On older Linux distributions, decode-dimms.pl was available as part of lm_sensors.
- OpenBSD has included a driver (spdmem(4)) since version 4.3 to provide information about memory modules. The driver was ported from NetBSD, where it is available since release 5.0.
- Coreboot reads and uses SPD information to initialize all memory controllerMemory controllerThe memory controller is a digital circuit which manages the flow of data going to and from the main memory. It can be a separate chip or integrated into another chip, such as on the die of a microprocessor...
s in a computer with timing, size and other properties.
- On WindowsMicrosoft WindowsMicrosoft Windows is a series of operating systems produced by Microsoft.Microsoft introduced an operating environment named Windows on November 20, 1985 as an add-on to MS-DOS in response to the growing interest in graphical user interfaces . Microsoft Windows came to dominate the world's personal...
systems, there are programs like HWiNFO32, CPU-Z and Speccy which are capable of reading and displaying DRAM module information from SPD.
Chipset-independent reading and writing of SPD information is done by accessing the memory's EEPROM directly with eeprom programmer hardware and software.
- A not so common use for old laptops is as generic SMBus readers, as the internal EEPROM on the module can be disabled once the BIOS has read it so the bus is essentially available for use.
The method used is to de-assert the /CE line so the internal memory shuts down, allowing the external device to access the SMBus.
Once this is done, a custom Linux build or DOS application can then access the external device; a common use is recovering data from LCD panel memory chips in order to retrofit a generic panel into a proprietary laptop.
On older equipment
Some older equipment require the use of SIMMSIMM
A SIMM, or single in-line memory module, is a type of memory module containing random access memory used in computers from the early 1980s to the late 1990s. It differs from a dual in-line memory module , the most predominant form of memory module today, in that the contacts on a SIMM are redundant...
s with SPD (more commonly called simply presence detect or PD). Some of this equipment uses non-standard PD coding; IBM
IBM
International Business Machines Corporation or IBM is an American multinational technology and consulting corporation headquartered in Armonk, New York, United States. IBM manufactures and sells computer hardware and software, and it offers infrastructure, hosting and consulting services in areas...
computers and Hewlett-Packard
Hewlett-Packard
Hewlett-Packard Company or HP is an American multinational information technology corporation headquartered in Palo Alto, California, USA that provides products, technologies, softwares, solutions and services to consumers, small- and medium-sized businesses and large enterprises, including...
LaserJet
LaserJet
LaserJet as a brand name identifies the line of dry electrophotographic laser printers marketed by the American computer-company Hewlett-Packard . The HP LaserJet was the world's first desktop laser printer.-Technology:...
and other printers in particular. While old computers are rarely found, many old Laserjet printers are in use. Discontinued HP memory modules are officially recommended, but any 72-pin SIMM module within the capacity range supported by the printer and with the correct PD code should work. All printers will work with FPM (Fast Page Mode) memory; it is reported that some, but not all, will work with EDO memory. It is fairly easy to solder wires to the PD pins to make non-HP modules work. HP printers of this type specify that RAM with an access time of or slower to be used; this is likely due to a limitation of the encoding in the PD data. Faster RAM can be used, but the PD encoded data should indicate a speed of .
External links
- Serial Presence Detect Standard, General Standard
- SPD Rev1.0 for DDR SDRAM
- SPD Rev1.2 for DDR2 SDRAM
- SPD Rev1.3 for DDR2 SDRAM
- SPECIALITY DDR2-1066 SDRAM
- Linux package i2c-tools
- Instructions on how to use lm-sensors or i2c-tools to read the data: http://ornellas.apanela.com/dokuwiki/pub:spd