NCSim
Encyclopedia
Incisive is a suite of tools from Cadence Design Systems
Cadence Design Systems
Cadence Design Systems, Inc is an electronic design automation software and engineering services company, founded in 1988 by the merger of SDA Systems and ECAD, Inc...

 related to the design and verification of ASIC
ASIC
ASIC may refer to:* Application-specific integrated circuit, an integrated circuit developed for a particular use, as opposed to a customised general-purpose device.* ASIC programming language, a dialect of BASIC...

s, SoC
SOC
SOC or SoC may refer to:Social Networking / Entertainment* Soc.TV, an internet based, social television network* Soldier of ChristBusiness* Sirte Oil Company* South Oil CompanyScience and technology...

s, and FPGAs. Incisive is commonly referred to by the name NCSim in reference to the core simulation engine. In the late 1990s, the tool suite was known as ldv (logic design and verification).

Depending on the design requirements, Incisive has many different bundling options of the following tools:
!Tool!!command!!description
|-
| NC Verilog
| ncvlog
| Compiler for Verilog
Verilog
In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...

 95, Verilog 2001 and SystemVerilog
SystemVerilog
In the semiconductor and electronic design industry, SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog.-History:...


|-
| NC VHDL
| ncvhdl
| Compiler for VHDL 87, VHDL 93
|-
| NC SystemC
| ncsc
| Compiler for SystemC
SystemC
SystemC is a set of C++ classes and macros which provide an event-driven simulation kernel in C++ . These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax...


|-
| NC Elaborator
| ncelab
| Unified linker / elaborator for Verilog, VHDL, and SystemC libraries. Generates a simulation object file referred to as a snapshot image.
|-
| NC Sim
| ncsim
| Unified simulation engine for Verilog, VHDL, and SystemC. Loads snapshot images generated by NC Elaborator. This tool can be run in GUI mode or batch command-line mode. In GUI mode, ncsim is similar to the debug features of ModelSim's vsim.
|-
| Sim Vision
| simvision
| A standalone graphical waveform viewer and netlist tracer. This is very similar to Novas Software
Novas Software
Novas Software was a company founded in 1996 by Dr. Paul Huang to address the ongoing problem of debugging chip designs. Novas was purchased by Taiwan-based EDA company SpringSoft in May 2008. Prior to its purchase, Novas was partly owned by SpringSoft, which developed the underlying debug...

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