POWER6
Encyclopedia
The POWER6 is a microprocessor
developed by IBM
that implemented the Power ISA v.2.03. When it became available in systems in 2007, it succeeded the POWER5+ as IBM's flagship Power microprocessor. It is part of the eCLipz project, said to have a goal of converging IBM's server hardware where practical (hence "ipz" in the acronym: iSeries, pSeries, and zSeries
).
(ISSCC) in February 2006, and additional details were added at the Microprocessor Forum in October 2006http://www.in-stat.com/FallMPF/06/ and at the next ISSCC in February 2007. It was formally announced on May 21, 2007.http://www-03.ibm.com/press/us/en/pressrelease/21580.wss It was released on June 8, 2007 at speeds of 3.5, 4.2 and 4.7 GHz, but the company has noted prototypes have reached 6 GHz. POWER6 reached first silicon in the middle of 2005, and was bumped to 5.0 GHz in May 2008 with the introduction P595.
(SMT). The POWER6 has approximately 790 million transistors and is 341 mm2 large fabricated on a 65 nm
process. A notable difference from POWER5
is that the POWER6 executes instructions in-order instead of out-of-order
. This change often requires software to be recompiled for optimal performance, but the POWER6 still achieves significant performance improvements over the POWER5+ even with unmodified software, according to the lead engineer on the POWER6 project.
POWER6 also takes advantage of ViVA-2
, Virtual Vector Architecture, which enables the combination of several POWER6 nodes to act as a single vector processor
.
Each core has two integer units
, two binary
floating-point unit
s, an AltiVec
unit, and a novel decimal
floating-point unit. The binary floating-point unit incorporates “many microarchitectures, logic, circuit, latch and integration techniques to achieve [a] 6-cycle, 13-FO4
pipeline,” according to a company paper. Unlike the servers from IBM's competitors, the POWER6 has hardware support for IEEE 754 decimal arithmetic and includes the first decimal floating-point unit integrated in silicon. More than 50 new floating point instructions handle the decimal math and conversions between binary and decimal. This feature was also added to the z10
microprocessor featured in the System z10
.
Each core has a 64 KB, four-way set-associative instruction cache and a 64 KB data cache of an eight-way set-associative design with a two-stage pipeline supporting two independent 32-bit reads or one 64-bit write per cycle. Each core has semi-private 4 MiB
unified L2 cache, where the cache is assigned a specific core, but the other has a fast access to it. The two cores share a 32 MiB L3 cache which is off die, using an 80 GB/s bus.
POWER6 can connect to up to 31 other processors using two inter node links (50 GB/s), and supports up to 10 logical partitions per core (up to a limit of 254 per system). There is an interface to a service processor that monitors and adjusts performance and power according to set parameters.
IBM also makes use of a 5 GHz duty-cycle correction clock distribution network for the processor. In the network, the company implements a copper distribution wire that is 3 µm wide and 1.2 µm thick. The POWER6 design uses dual power supplies, a logic supply in the 0.8-to-1.2 Volt range and an SRAM power supply at about 150-mV higher.
The thermal characteristics of POWER6 are similar to that of the POWER5
. Dr Frank Soltis
, an IBM chief scientist, said IBM had solved power leakage problems associated with high frequency by using a combination of 90 nm
and 65 nm parts in the POWER6 design.
systems since October 2008. It added more memory keys for secure memory partition, a feature taken from IBM's mainframe processors
.
For example, the 520 Express is marketed to small businesses while the Power 595 is marketed for large, multi-environment data centers.
The main difference between the Express and Enterprise models is that the latter include Capacity Upgrade on Demand (CUoD) capabilities and hot-pluggable processor and memory "books". All Power systems are noted for their excellent scalability and storage capabilities.
IBM also offers four POWER6 based blade server
s.http://www-03.ibm.com/systems/power/hardware/blades/index.html Specifications are shown in the table below.
All blades support AIX, i, and Linux. The BladeCenter S and H chassis is supported for blades running AIX, i, and Linux. The BladeCenter E, HT, and T chassis support blades running AIX and Linux but not i.
At the SuperComputing 2007 (SC07) conference in Reno a new water-cooled Power 575 was revealed. The 575 is composed of 2U "nodes" each with 32 POWER6 cores at 4.7 GHz with up to 256 GB of RAM. Up to 448 cores can be installed in a single frame.
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
developed by IBM
IBM
International Business Machines Corporation or IBM is an American multinational technology and consulting corporation headquartered in Armonk, New York, United States. IBM manufactures and sells computer hardware and software, and it offers infrastructure, hosting and consulting services in areas...
that implemented the Power ISA v.2.03. When it became available in systems in 2007, it succeeded the POWER5+ as IBM's flagship Power microprocessor. It is part of the eCLipz project, said to have a goal of converging IBM's server hardware where practical (hence "ipz" in the acronym: iSeries, pSeries, and zSeries
ZSeries
IBM System z, or earlier IBM eServer zSeries, is a brand name designated by IBM to all its mainframe computers.In 2000, IBM rebranded the existing System/390 to IBM eServer zSeries with the e depicted in IBM's red trademarked symbol, but because no specific machine names were changed for...
).
History
POWER6 was described at the International Solid-State Circuits ConferenceInternational Solid-State Circuits Conference
International Solid-State Circuits Conference is a global forum for presentation of advances in solid-state circuits and Systems-on-a-Chip. The Conference offers a unique opportunity for engineers working at the cutting edge of IC design to maintain technical currency, and to network with leading...
(ISSCC) in February 2006, and additional details were added at the Microprocessor Forum in October 2006http://www.in-stat.com/FallMPF/06/ and at the next ISSCC in February 2007. It was formally announced on May 21, 2007.http://www-03.ibm.com/press/us/en/pressrelease/21580.wss It was released on June 8, 2007 at speeds of 3.5, 4.2 and 4.7 GHz, but the company has noted prototypes have reached 6 GHz. POWER6 reached first silicon in the middle of 2005, and was bumped to 5.0 GHz in May 2008 with the introduction P595.
Description
The POWER6 is a dual-core processor. Each core is capable of two-way simultaneous multithreadingSimultaneous multithreading
Simultaneous multithreading, often abbreviated as SMT, is a technique for improving the overall efficiency of superscalar CPUs with hardware multithreading...
(SMT). The POWER6 has approximately 790 million transistors and is 341 mm2 large fabricated on a 65 nm
65 nanometer
The 65 nm process is an advanced lithographic node used in volume CMOS semiconductor fabrication. Printed linewidths can reach as low as 25 nm on a nominally 65 nm process, while the pitch between two lines may be greater than 130 nm.. For comparison, cellular ribosomes are...
process. A notable difference from POWER5
POWER5
The POWER5 is a microprocessor developed and fabricated by IBM. It is an improved version of the highly successful POWER4. The principal improvements are support for simultaneous multithreading and an on-die memory controller...
is that the POWER6 executes instructions in-order instead of out-of-order
Out-of-order execution
In computer engineering, out-of-order execution is a paradigm used in most high-performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay...
. This change often requires software to be recompiled for optimal performance, but the POWER6 still achieves significant performance improvements over the POWER5+ even with unmodified software, according to the lead engineer on the POWER6 project.
POWER6 also takes advantage of ViVA-2
IBM ViVA
ViVA is a technology from IBM for coupling together multiple scalar floating point units to act as a single vector processor...
, Virtual Vector Architecture, which enables the combination of several POWER6 nodes to act as a single vector processor
Vector processor
A vector processor, or array processor, is a central processing unit that implements an instruction set containing instructions that operate on one-dimensional arrays of data called vectors. This is in contrast to a scalar processor, whose instructions operate on single data items...
.
Each core has two integer units
Arithmetic logic unit
In computing, an arithmetic logic unit is a digital circuit that performs arithmetic and logical operations.The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers...
, two binary
Binary code
A binary code is a way of representing text or computer processor instructions by the use of the binary number system's two-binary digits 0 and 1. This is accomplished by assigning a bit string to each particular symbol or instruction...
floating-point unit
Floating point unit
A floating-point unit is a part of a computer system specially designed to carry out operations on floating point numbers. Typical operations are addition, subtraction, multiplication, division, and square root...
s, an AltiVec
AltiVec
AltiVec is a floating point and integer SIMD instruction set designed and owned by Apple, IBM and Freescale Semiconductor, formerly the Semiconductor Products Sector of Motorola, , and implemented on versions of the PowerPC including Motorola's G4, IBM's G5 and POWER6 processors, and P.A. Semi's...
unit, and a novel decimal
Decimal floating point
Decimal floating point arithmetic refers to both a representation and operations on decimal floating point numbers. Working directly with decimal fractions can avoid the rounding errors that otherwise typically occur when converting between decimal fractions and binary fractions.The...
floating-point unit. The binary floating-point unit incorporates “many microarchitectures, logic, circuit, latch and integration techniques to achieve [a] 6-cycle, 13-FO4
FO4
Fan-out of 4 is a process independent delay metric used in digital CMOS technologies.Fan out = Cload / CinCload = total MOS gate capacitance driven by the logic gate under considerationCin = the MOS gate capacitance of the logic gate under consideration...
pipeline,” according to a company paper. Unlike the servers from IBM's competitors, the POWER6 has hardware support for IEEE 754 decimal arithmetic and includes the first decimal floating-point unit integrated in silicon. More than 50 new floating point instructions handle the decimal math and conversions between binary and decimal. This feature was also added to the z10
IBM z10 (microprocessor)
The z10 is a microprocessor chip made by IBM for their System z10 mainframe computers, released February 26, 2008. It was called "z6" during development.- Description :...
microprocessor featured in the System z10
IBM System z10
IBM System z10 is a line of IBM mainframes. The z10 Enterprise Class was announced on February 26, 2008. On October 21, 2008, IBM announced the z10 Business Class , a scaled down version of the z10 EC...
.
Each core has a 64 KB, four-way set-associative instruction cache and a 64 KB data cache of an eight-way set-associative design with a two-stage pipeline supporting two independent 32-bit reads or one 64-bit write per cycle. Each core has semi-private 4 MiB
MIB
MIB may refer to any of several concepts:* Master of International Business, a postgraduate business degree* Melayu Islam Beraja, the adopted national philosophy of Brunei* Motion induced blindness, a visual illusion in peripheral vision...
unified L2 cache, where the cache is assigned a specific core, but the other has a fast access to it. The two cores share a 32 MiB L3 cache which is off die, using an 80 GB/s bus.
POWER6 can connect to up to 31 other processors using two inter node links (50 GB/s), and supports up to 10 logical partitions per core (up to a limit of 254 per system). There is an interface to a service processor that monitors and adjusts performance and power according to set parameters.
IBM also makes use of a 5 GHz duty-cycle correction clock distribution network for the processor. In the network, the company implements a copper distribution wire that is 3 µm wide and 1.2 µm thick. The POWER6 design uses dual power supplies, a logic supply in the 0.8-to-1.2 Volt range and an SRAM power supply at about 150-mV higher.
The thermal characteristics of POWER6 are similar to that of the POWER5
POWER5
The POWER5 is a microprocessor developed and fabricated by IBM. It is an improved version of the highly successful POWER4. The principal improvements are support for simultaneous multithreading and an on-die memory controller...
. Dr Frank Soltis
Frank Soltis
Frank Gerald Soltis , an American computer scientist, was IBM's Chief Scientist for the System i computers. Based on his Ph.D. research, his pioneering architecture of technology-independent machine interface and single-level store has appeared in these eight generations of IBM hardware: ...
, an IBM chief scientist, said IBM had solved power leakage problems associated with high frequency by using a combination of 90 nm
90 nanometer
The 90 nm process refers to the level of CMOS process technology that was reached in the 2002–2003 timeframe, by most leading semiconductor companies, like Intel, AMD, Infineon, Texas Instruments, IBM, and TSMC....
and 65 nm parts in the POWER6 design.
POWER6+
The slightly enhanced POWER6+ was introduced in April 2009, but had been shipping in Power 560 and 570IBM Power Systems
Power Systems is the name of IBM's Power Architecture-based server line.Before the Power Systems line was announced on April 2, 2008, IBM had two distinct Power-based lines: the System i running IBM i - and the System p series running AIX or Linux.- History :IBM had two discrete Power Architecture...
systems since October 2008. It added more memory keys for secure memory partition, a feature taken from IBM's mainframe processors
Z/Architecture
z/Architecture, initially and briefly called ESA Modal Extensions , refers to IBM's 64-bit computing architecture for IBM mainframe computers. IBM introduced its first z/Architecture-based system, the zSeries Model 900, in late 2000. Later z/Architecture systems include the IBM z800, z990, z890,...
.
Products
, the range of POWER6 systems includes "Express" models (the 520, 550 and 560) and Enterprise models (the 570 and 595).http://www-03.ibm.com/systems/power/hardware/ The various system models are designed to serve any sized business.For example, the 520 Express is marketed to small businesses while the Power 595 is marketed for large, multi-environment data centers.
The main difference between the Express and Enterprise models is that the latter include Capacity Upgrade on Demand (CUoD) capabilities and hot-pluggable processor and memory "books". All Power systems are noted for their excellent scalability and storage capabilities.
| Name | Number of sockets | Number of cores | CPU clock frequency |
|---|---|---|---|
| 520 Express | 2 | 4 | 4.2 GHz or 4.7 GHz |
| 550 Express | 4 | 8 | 4.2 GHz or 5.0 GHz |
| 560 Express | 8 | 16 | 3.6 GHz |
| 570 | 8 | 16 | 4.4 GHz or 5.0 GHz |
| 570 | 16 | 32 | 4.2 GHz |
| 575 | 16 | 32 | 4.7 GHz |
| 595 | 32 | 64 | 4.2 GHz or 5.0 GHz |
IBM also offers four POWER6 based blade server
Blade server
A blade server is a stripped down server computer with a modular design optimized to minimize the use of physical space and energy. Whereas a standard rack-mount server can function with a power cord and network cable, blade servers have many components removed to save space, minimize power...
s.http://www-03.ibm.com/systems/power/hardware/blades/index.html Specifications are shown in the table below.
| Name | Number of cores | CPU clock frequency | Blade slots required |
|---|---|---|---|
| BladeCenter JS12 | 2 | 3.8 GHz | 1 |
| BladeCenter JS22 | 4 | 4.0 GHz | 1 |
| BladeCenter JS23 | 4 | 4.2 GHz | 1 |
| BladeCenter JS43 | 8 | 4.2 GHz | 2 |
All blades support AIX, i, and Linux. The BladeCenter S and H chassis is supported for blades running AIX, i, and Linux. The BladeCenter E, HT, and T chassis support blades running AIX and Linux but not i.
At the SuperComputing 2007 (SC07) conference in Reno a new water-cooled Power 575 was revealed. The 575 is composed of 2U "nodes" each with 32 POWER6 cores at 4.7 GHz with up to 256 GB of RAM. Up to 448 cores can be installed in a single frame.
| Name | Number of cores | CPU clock frequency | Number of controllers |
|---|---|---|---|
| DS8700 | 2, 4 | 4.7 GHz | 1, 2 |
| DS8800 | 2, 4, 8 | 5.0 GHz | 1, 2 |
See also
- IBM POWERIBM POWERPOWER is a reduced instruction set computer instruction set architecture developed by IBM. The name is an acronym for Performance Optimization With Enhanced RISC....
- Power ArchitecturePower ArchitecturePower Architecture is a broad term to describe similar RISC instruction sets for microprocessors developed and manufactured by such companies as IBM, Freescale, AMCC, Tundra and P.A. Semi...
- POWER7POWER7POWER7 is a Power Architecture microprocessor released in 2010 that succeeded the POWER6. POWER7 was developed by IBM at several sites including IBM's Rochester, MN; Austin, TX; Essex Junction, Vermont; T. J. Watson Research Center, NY; Bromont, QC and Böblingen, Germany laboratories...
- z10IBM z10 (microprocessor)The z10 is a microprocessor chip made by IBM for their System z10 mainframe computers, released February 26, 2008. It was called "z6" during development.- Description :...
, a mainframeMainframe computerMainframes are powerful computers used primarily by corporate and governmental organizations for critical applications, bulk data processing such as census, industry and consumer statistics, enterprise resource planning, and financial transaction processing.The term originally referred to the...
processor sharing much technology with the POWER6.
External links
- IBM Press Kit
- IBM's Power6 doubles speed
- IBM Unleashes World's Fastest Chip in Powerful New Computer, 21 May 2007
- InformationWeek report on the Power6 announcement
- Real World Tech, Dec 19, 2005
- InformationWeek, Feb 6, 2006
- C|Net, Oct 10, 2006
- Heise Online, Oct 12, 2006
- Real World Tech, Oct 16, 2006
- Arstechnica, Oct 19, 2006
- Arstechnica, Feb 12, 2007
- Arstechnica, May 21, 2007
- The POWER6 microarchitecture, November 2007. IBM.com
Recommended reading
- POWER Roadmap, IBM, Oct 2006
- IBM POWER6 Reliability, IBM, Nov 2007
- IBM POWER6 microprocessor physical design and design methodology, IBM, Nov 2007
- EnergyScale for IBM POWER6 microprocessor based systems, IBM, Nov 2007
- System power management support in the IBM POWER6 microprocessor, IBM, Nov 2007
- IBM POWER6 microarchitecture, IBM, Nov 2007
- IBM POWER6 SRAM arrays, IBM, Nov 2007
- IBM POWER6 accelerators: VMX and DFU, IBM, Nov 2007
- "POWER: The Sixth Generation". (30 October 2006). Microprocessor Report.