Power network design (IC)
Encyclopedia
In integrated circuit
s, electrical power is distributed to the components of the chip over a network of conductors on the chip. Power network design includes the analysis and design of such networks. As in all engineering, this involves tradeoffs - the network must have adequate performance, be sufficiently reliable, but should not use more resources than required.
locations to all devices in a design.
Shrinking device dimension
s, faster switching frequencies and increasing power consumption in deep sub-micrometre technologies cause large switching currents to flow in the power and ground networks which degrade performance and reliability. A robust power distribution network is essential to ensure reliable operation of circuits on a chip. Power supply integrity verification is a critical concern in high-performance designs. Due to the resistance
of the interconnects constituting the network, there is a voltage drop across the network, commonly referred to as the IR-drop. The package supplies currents to the pads of the power grid either by means of package leads in wire-bond chips or through C4 bump arrays in flip chip
technology. Although the resistance of package is quite small, the inductance
of package leads is significant which causes a voltage drop at the pad locations due to the time varying current drawn by the devices on die. This voltage drop is referred to as the di/dt-drop. Therefore the voltage seen at the devices is the supply voltage minus the IR-drop and di/dt-drop.
Excessive voltage drops in the power grid reduce switching speeds
and noise margins of circuits, and inject noise which might lead to functional failures
. High average current densities lead to undesirable wearing out of metal wires due to electromigration
(EM). Therefore, the challenge in the design of a power distribution network is in achieving excellent voltage regulation at the consumption points notwithstanding the wide fluctuations in power demand across the chip, and to build such a network using minimum area of the metal layers. These issues are prominent in high performance chips such as microprocessor
s, since large amounts of power have to be distributed through a hierarchy of many metal layers.
A robust power distribution network is vital in meeting performance guarantees and ensuring reliable operation.
Capacitance between power and ground distribution networks, referred to as decoupling capacitor
s or decaps, acts as local charge storage and is helpful in mitigating the voltage drop at supply points. Parasitic capacitance between metal wires of supply lines, device capacitance of the non-switching devices, and capacitance between N-well and substrate, occur as implicit decoupling capacitance in a power distribution network. Unfortunately, this implicit decoupling capacitance is sometimes not enough to constrain the voltage drop within safe bounds and designers often have to add intentional explicit decoupling capacitance structures on the die at strategic locations. These explicitly added decoupling capacitances are not free and increase the area and leakage power consumption of the chip. Parasitic interconnect resistance
, decoupling capacitance
and package/interconnect inductance
form a complex RLC circuit
which has its own resonance frequency. If the resonance frequency lies close to the operating frequency of the design, large voltage drops can develop in the grid.
The crux of the problem in designing a power grid is that there are many unknowns until the very end of the design cycle. Nevertheless, decisions about the structure, size and layout of the power grid have to be made at very early stages when a large part of the chip design has not even begun. Unfortunately, most commercial tools focus on post-layout verification of the power grid when the entire chip design is complete and detailed information about the parasitics of the power and ground lines and the currents drawn by the transistors are known. Power grid problems revealed at this stage are usually very difficult or expensive to fix, so the preferred methodologeis help to design an initial power grid and refine it progressively at various design stages.
Due to the growth in power consumption and switching speeds of modern high performance microprocessors, the di/dt effects are becoming a growing concern in high speed designs. Clock gating
, which is a preferred scheme for power management of high performance designs, can cause rapid surges in current demands of macro-blocks and increase di/dt effects. Designers rely on the on-chip parasitic capacitances and intentionally added decoupling capacitors to counteract the di/dt variations in the voltage. But it is necessary to model accurately the inductance and capacitance of the package and chip and analyze the grid with such models, as otherwise the amount of decoupling to be added might be underestimated or overestimated. Also it is necessary to maintain the efficiency of the analysis even when including these detailed models.
A critical issue in the analysis of power grids is the large size of the network (typically millions of nodes in a state-of-the-art microprocessor). Simulating all the non-linear devices in the chip together with the power grid is computationally infeasible. To
make the size manageable, the simulation is done in two steps. First, the non-linear devices are simulated assuming perfect supply
voltages and the currents drawn by the devices are measured. Next, these devices are modeled as independent time-varying current
sources for simulating the power grid and the voltage drops at the transistors are measured. Since voltage drops are typically less than 10% of the power supply voltage, the error incurred by ignoring the interaction between the device currents and the supply voltage is small. By doing these two steps, the power grid analysis problem reduces to solving a linear network which is still quite large. To further reduce the network size, we can exploit the hierarchy in the power distribution models.
Note that the circuit currents are not independent due to signal correlations between blocks. This is addressed by deriving the inputs for individual blocks of the chip from the results of logic simulation
using a common set of chip-wide input patterns. An important issue in power grid analysis is to determine what these input patterns should be. For IR-drop analysis, patterns that produce maximum instantaneous currents are required, whereas for electromigration purposes, patterns producing large sustained (average) currents are of interest.
Power grid analysis can be classified into input vector dependent methods and vectorless methods. The input vector pattern dependent methods employ search techniques to find a set of input patterns which cause the worst drop in the grid. A number of methods have been proposed in literature which use genetic algorithms or other search techniques to find vectors or a pattern of vectors that maximize the total current drawn from the supply network. Input vector-pattern dependent approaches are computationally intensive and are limited to circuit blocks rather than full-chip analysis. Furthermore, these approaches are inherently optimistic, underestimating the voltage drop and thus letting some of the supply noise problems go unnoticed. The vectorless approaches, on the other hand, aim to compute an upper bound on the worst-case drop in an efficient manner.
These approaches have the advantage of being fast and conservative, but are
sometimes too conservative, leading to overdesign.
Most of the literature on power network analysis deals with the
issue of computing the worst voltage drops in the power network.
Electromigration is an equally serious concern,
but is attacked with
almost identical methods. Instead of the voltage at each node, EM
analysis solves for current in each branch, and instead of a voltage
limit, there is a current limit per wire, depending on its layer and
width.
Other IC applications may use only a portions of the flows mentioned here.
A gate array
or field programmable gate array (FPGA) designer, for example, will
only do only the design stages, since the detailed usage of these
parts is not known when the power supply must be designed. Likewise, a user
of FPGAs or gate arrays will only use the analysis portion, as the design
is already fixed.
Integrated circuit
An integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...
s, electrical power is distributed to the components of the chip over a network of conductors on the chip. Power network design includes the analysis and design of such networks. As in all engineering, this involves tradeoffs - the network must have adequate performance, be sufficiently reliable, but should not use more resources than required.
Introduction
The power distribution network distributes power and ground voltages from padWire bonding
Wire bonding is the primary method of making interconnections between an integrated circuit and a printed circuit board during semiconductor device fabrication. Although less common, wire bonding can be used to connect an IC to other electronics or to connect from one PCB to another...
locations to all devices in a design.
Shrinking device dimension
Moore's Law
Moore's law describes a long-term trend in the history of computing hardware: the number of transistors that can be placed inexpensively on an integrated circuit doubles approximately every two years....
s, faster switching frequencies and increasing power consumption in deep sub-micrometre technologies cause large switching currents to flow in the power and ground networks which degrade performance and reliability. A robust power distribution network is essential to ensure reliable operation of circuits on a chip. Power supply integrity verification is a critical concern in high-performance designs. Due to the resistance
Electrical resistance
The electrical resistance of an electrical element is the opposition to the passage of an electric current through that element; the inverse quantity is electrical conductance, the ease at which an electric current passes. Electrical resistance shares some conceptual parallels with the mechanical...
of the interconnects constituting the network, there is a voltage drop across the network, commonly referred to as the IR-drop. The package supplies currents to the pads of the power grid either by means of package leads in wire-bond chips or through C4 bump arrays in flip chip
Flip chip
Flip chip, also known as Controlled Collapse Chip Connection or its acronym, C4, is a method for interconnecting semiconductor devices, such as IC chips and Microelectromechanical systems , to external circuitry with solder bumps that have been deposited onto the chip pads...
technology. Although the resistance of package is quite small, the inductance
Inductance
In electromagnetism and electronics, inductance is the ability of an inductor to store energy in a magnetic field. Inductors generate an opposing voltage proportional to the rate of change in current in a circuit...
of package leads is significant which causes a voltage drop at the pad locations due to the time varying current drawn by the devices on die. This voltage drop is referred to as the di/dt-drop. Therefore the voltage seen at the devices is the supply voltage minus the IR-drop and di/dt-drop.
Excessive voltage drops in the power grid reduce switching speeds
Delay calculation
Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached to it. By contrast, static timing analysis computes the delays of entire paths, using delay calculation to determine the delay of each gate and...
and noise margins of circuits, and inject noise which might lead to functional failures
Signal integrity
Signal integrity or SI is a set of measures of the quality of an electrical signal. In digital electronics, a stream of binary values is represented by a voltage waveform. However, digital signals are fundamentally analog in nature, and all signals are subject to effects such as noise,...
. High average current densities lead to undesirable wearing out of metal wires due to electromigration
Electromigration
Electromigration is the transport of material caused by the gradual movement of the ions in a conductor due to the momentum transfer between conducting electrons and diffusing metal atoms. The effect is important in applications where high direct current densities are used, such as in...
(EM). Therefore, the challenge in the design of a power distribution network is in achieving excellent voltage regulation at the consumption points notwithstanding the wide fluctuations in power demand across the chip, and to build such a network using minimum area of the metal layers. These issues are prominent in high performance chips such as microprocessor
Microprocessor
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit, or at most a few integrated circuits. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and...
s, since large amounts of power have to be distributed through a hierarchy of many metal layers.
A robust power distribution network is vital in meeting performance guarantees and ensuring reliable operation.
Capacitance between power and ground distribution networks, referred to as decoupling capacitor
Decoupling capacitor
A decoupling capacitor is a capacitor used to decouple one part of an electrical network from another. Noise caused by other circuit elements is shunted through the capacitor, reducing the effect they have on the rest of the circuit....
s or decaps, acts as local charge storage and is helpful in mitigating the voltage drop at supply points. Parasitic capacitance between metal wires of supply lines, device capacitance of the non-switching devices, and capacitance between N-well and substrate, occur as implicit decoupling capacitance in a power distribution network. Unfortunately, this implicit decoupling capacitance is sometimes not enough to constrain the voltage drop within safe bounds and designers often have to add intentional explicit decoupling capacitance structures on the die at strategic locations. These explicitly added decoupling capacitances are not free and increase the area and leakage power consumption of the chip. Parasitic interconnect resistance
Electrical resistance
The electrical resistance of an electrical element is the opposition to the passage of an electric current through that element; the inverse quantity is electrical conductance, the ease at which an electric current passes. Electrical resistance shares some conceptual parallels with the mechanical...
, decoupling capacitance
Capacitance
In electromagnetism and electronics, capacitance is the ability of a capacitor to store energy in an electric field. Capacitance is also a measure of the amount of electric potential energy stored for a given electric potential. A common form of energy storage device is a parallel-plate capacitor...
and package/interconnect inductance
Inductance
In electromagnetism and electronics, inductance is the ability of an inductor to store energy in a magnetic field. Inductors generate an opposing voltage proportional to the rate of change in current in a circuit...
form a complex RLC circuit
RLC circuit
An RLC circuit is an electrical circuit consisting of a resistor, an inductor, and a capacitor, connected in series or in parallel. The RLC part of the name is due to those letters being the usual electrical symbols for resistance, inductance and capacitance respectively...
which has its own resonance frequency. If the resonance frequency lies close to the operating frequency of the design, large voltage drops can develop in the grid.
The crux of the problem in designing a power grid is that there are many unknowns until the very end of the design cycle. Nevertheless, decisions about the structure, size and layout of the power grid have to be made at very early stages when a large part of the chip design has not even begun. Unfortunately, most commercial tools focus on post-layout verification of the power grid when the entire chip design is complete and detailed information about the parasitics of the power and ground lines and the currents drawn by the transistors are known. Power grid problems revealed at this stage are usually very difficult or expensive to fix, so the preferred methodologeis help to design an initial power grid and refine it progressively at various design stages.
Due to the growth in power consumption and switching speeds of modern high performance microprocessors, the di/dt effects are becoming a growing concern in high speed designs. Clock gating
Clock gating
Clock gating is a power-saving technique used in many synchronous circuits-Description:Clock gating is a popular technique used in many synchronous circuits for reducing dynamic power dissipation. Clock gating saves power by adding more logic to a circuit to prune the clock tree...
, which is a preferred scheme for power management of high performance designs, can cause rapid surges in current demands of macro-blocks and increase di/dt effects. Designers rely on the on-chip parasitic capacitances and intentionally added decoupling capacitors to counteract the di/dt variations in the voltage. But it is necessary to model accurately the inductance and capacitance of the package and chip and analyze the grid with such models, as otherwise the amount of decoupling to be added might be underestimated or overestimated. Also it is necessary to maintain the efficiency of the analysis even when including these detailed models.
A critical issue in the analysis of power grids is the large size of the network (typically millions of nodes in a state-of-the-art microprocessor). Simulating all the non-linear devices in the chip together with the power grid is computationally infeasible. To
make the size manageable, the simulation is done in two steps. First, the non-linear devices are simulated assuming perfect supply
voltages and the currents drawn by the devices are measured. Next, these devices are modeled as independent time-varying current
sources for simulating the power grid and the voltage drops at the transistors are measured. Since voltage drops are typically less than 10% of the power supply voltage, the error incurred by ignoring the interaction between the device currents and the supply voltage is small. By doing these two steps, the power grid analysis problem reduces to solving a linear network which is still quite large. To further reduce the network size, we can exploit the hierarchy in the power distribution models.
Note that the circuit currents are not independent due to signal correlations between blocks. This is addressed by deriving the inputs for individual blocks of the chip from the results of logic simulation
Logic simulation
Logic simulation is the use of a computer program to simulate the operation of a digital circuit. Logic simulation is the primary tool used for verifying the logical correctness of a hardware design. In many cases logic simulation is the first activity performed in the process of taking a hardware...
using a common set of chip-wide input patterns. An important issue in power grid analysis is to determine what these input patterns should be. For IR-drop analysis, patterns that produce maximum instantaneous currents are required, whereas for electromigration purposes, patterns producing large sustained (average) currents are of interest.
Power grid analysis can be classified into input vector dependent methods and vectorless methods. The input vector pattern dependent methods employ search techniques to find a set of input patterns which cause the worst drop in the grid. A number of methods have been proposed in literature which use genetic algorithms or other search techniques to find vectors or a pattern of vectors that maximize the total current drawn from the supply network. Input vector-pattern dependent approaches are computationally intensive and are limited to circuit blocks rather than full-chip analysis. Furthermore, these approaches are inherently optimistic, underestimating the voltage drop and thus letting some of the supply noise problems go unnoticed. The vectorless approaches, on the other hand, aim to compute an upper bound on the worst-case drop in an efficient manner.
These approaches have the advantage of being fast and conservative, but are
sometimes too conservative, leading to overdesign.
Most of the literature on power network analysis deals with the
issue of computing the worst voltage drops in the power network.
Electromigration is an equally serious concern,
but is attacked with
almost identical methods. Instead of the voltage at each node, EM
analysis solves for current in each branch, and instead of a voltage
limit, there is a current limit per wire, depending on its layer and
width.
Other IC applications may use only a portions of the flows mentioned here.
A gate array
Gate array
A gate array or uncommitted logic array is an approach to the design and manufacture of application-specific integrated circuits...
or field programmable gate array (FPGA) designer, for example, will
only do only the design stages, since the detailed usage of these
parts is not known when the power supply must be designed. Likewise, a user
of FPGAs or gate arrays will only use the analysis portion, as the design
is already fixed.