QsNet II is the latest generation of Quadrics Interconnect family products.
Quadrics

Quadrics

Quadrics was a supercomputer company formed in 1996 as a joint venture between Alenia Spazio and the technical team from Meiko Scientific. They produced hardware and software for clustering commodity computer systems into massively parallel systems. Their highpoint was in June 2003 when six out of...

 QsNetII interfaces to the host computer through the standard IO PCI

Peripheral Component Interconnect

Conventional PCI is a computer bus for attaching hardware devices in a computer...

-X bus.

Architecture

The architecture of the network interface has been developed to offload the entire task of interprocessor communication from the main processor, and to avoid the overhead of system calls for user process to user process messaging. QsNetII is designed for use within SMP

Symmetric multiprocessing

In computing, symmetric multiprocessing involves a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance. Most common multiprocessor systems today use an SMP architecture...

 systems — multiple, concurrent processes can utilise the network interface without any task switching overhead. A I/O processor offloads protocol handling from the main CPU. Local memory on the PCI card provides storage for buffers, translation tables and I/O adapter code. All the PCI bandwidth is available to data communication.

Components

QsNetII's core design is based on two ASICs: Elan4 and Elite4. Elan4 is a communication processor that forms the interface between a high-performance multistage network and a processing node with one or more CPUs. Elite4 is a switching component that can switch eight bidirectional communications links, each of which carrying data in both directions simultaneously at 1.3 GB

Gigabyte

The gigabyte is a multiple of the unit byte for digital information storage. The prefix giga means 109 in the International System of Units , therefore 1 gigabyte is...

/s.

Topology

Quadrics QsNetII interconnect like its predecessor QsNet

QsNet

QsNet is a high speed interconnect designed by Quadrics used in HPC clusters, particularly Linux Beowulf Clusters. Although it can be used with TCP/IP; like SCI, Myrinet and Infiniband it is usually used with a communication API such as MPI or SHMEM called from a parallel program.The interconnect...

 uses a 'fat tree' topology, QsNetII scales up to 4096 nodes, each node might have multiple CPUs so that systems of >10,000 CPUs can be constructed. Multiple, parallel QsNet networks can be employed in a system to maintain the compute to communications ratio where high CPU count SMP nodes are employed.
The fat tree topology is resilient with large amounts of redundancy in the higher levels of the switch.

Latency and Bandwidth

Performance depends on platform used and configuration of the system, QsNetII MPI latency on standard AMD Opteron

Opteron

Opteron is AMD's x86 server and workstation processor line, and was the first processor which supported the AMD64 instruction set architecture . It was released on April 22, 2003 with the SledgeHammer core and was intended to compete in the server and workstation markets, particularly in the same...

 starts at 1.22 μs; Bandwidth on Intel Xeon Intel 64 is 912 MB

Megabyte

The megabyte is a multiple of the unit byte for digital information storage or transmission with two different values depending on context: bytes generally for computer memory; and one million bytes generally for computer storage. The IEEE Standards Board has decided that "Mega will mean 1 000...

/s.