SGI Origin 2000
Encyclopedia
The SGI Origin 2000, code named Lego, is a family of mid-range and high-end servers
developed and manufactured by SGI
and introduced in 1996 to succeed the SGI Challenge
and POWER Challenge
. At the time of introduction, these systems ran IRIX 6.4
and later, IRIX 6.5
. A variant of the Origin 2000 with graphics capability is known as the Onyx2
. An entry-level variant based on the same architecture but with a different hardware implementation is known as the Origin 200
. The Origin 2000 was succeeded by the Origin 3000 in July 2000, and was discontinued on 30 June 2002.
Note: The highest CPU count that the SGI marketed the Origin 2000/28000 was 128 CPUs. However, three Origin 2000 models were made that were capable of using 512 CPUs and 512 GB of memory, but these were never marketed as a system to customers. One of the 512-CPU Origin 2000 series was installed at SGI's facility in Eagan, Minnesota for test purposes and the other two were sold to NASA Ames Research Center in California for specialized scientific computing. The 512-CPU Origin 2800s cost roughly $40 million each and the delivery of the Origin 3000 systems, scalable up to 512 or 1024 CPUs at a lower price point per performance, made the 512-CPU Origin 2800 obsolete.
Several customers also bought 256-CPU Origin 2000 series systems, although it was never marketed as a product by SGI either.
The largest installation of SGI Origin 2000 series was ASCII Blue Mountain at Los Alamos National Labs. It included 48 Origin 2000 series 128-CPU systems all connected via HIPPI for a total of 6144 processors. At the time it was tested, it placed second on the TOP500
list of fastest computers in the world. Note that this test was completed only with 40 nodes with 128 CPUs each and recorded a sustained 1.6 teraflops. With all nodes connected, it was able to sustain 2.1 teraflops and peak of over 2.5 teraflops.
Los Alamos also had another 12 Origin 128-CPU systems (for a total of 1536 CPUs) as part of the same testing.
The Origin 2100 is mostly the same as the other models except that it is not upgradeable to other models. (unless the router cards, etc. were replaced)
. Each backplane forms a module that can contain four node boards, two router boards and twelve XIO
options. The modules are then mounted inside a deskside enclosure or a rack. Deskside enclosures can only contain one module, while racks can contain two. In configurations with more than two modules, multiple racks are used.
Figures specified are for maximum configurations.
S2MP (Scalable Shared-Memory Multiprocessing) architecture. The Origin 2000 uses NUMAlink (originally named CrayLink) for its system interconnect. The nodes are connected to router boards, which use NUMAlink cables to connect to other nodes through their routers. The NUMAlink's network topology is a bristled fat hypercube
. In configurations with more than 64 processors, a hierarchical fat hypercube network topology is used instead. Additional NUMAlink cables, called Xpress links can be installed between unused Standard Router ports to reduce latency and increase bandwidth. Xpress links can only be used in systems that have 16 or 32 processors, as these are the only configurations with a network topology that enables unused ports to be used in such a way.
The Null Router connects two nodes in the same module. A system using the Null Router cannot be expanded as there are no external connectors.
The Star Router can connect up to four nodes. It is always used in conjunction with a Standard Router to function correctly.
The Standard Router can connect up to 32 nodes. It contains the SPIDER ASIC, which serves as a router for the NUMAlink network. The SPIDER ASIC has six ports, each with a pair of unidirectional links, connected to a crossbar
which enables the ports to communicate with each other.
The Meta Router is used in conjunction with Standard Routers to connect more than 32 nodes. It can connect up to 64 nodes.
that contains one or two processors, the main memory, the directory memory and the Hub ASIC. The node board plugs into the backplane through a 300-pad CPOP (Compression Pad-on-Pad) connector. The connector actually combines two connections, one to the NUMAlink router network and another to the XIO I/O subsystem.
processors clocked at 180 MHz with 1 MB secondary cache(s). A high-end model with two 195 MHz R10000 processors with 4 MB secondary caches was also available. In February 1998, the IP31 board was introduced with two 250 MHz R10000 processors with 4 MB secondary caches. Later, the IP31 board was upgraded to support two 300, 350 or 400 MHz R12000 processors. The 300 and 400 MHz models had 8 MB L2 caches, while the 350 MHz model had 4 MB L2 caches. Near the end of its life, a variant of the IP31 board that could utilize the 500 MHz R14000 with 8 MB L2 caches was made available.
DIMM
s with capacities of 16, 32, 64 and 256 MB. Because the memory bus is 144 bits wide (128 bits for data and 16 bits for ECC), memory modules are inserted in pairs. Directory memory, which contains information on the contents of remote caches for maintaining cache coherency
, must be used in configurations with more than 32 processors as the Origin 2000 uses a distributed shared memory model. The directory memory is contained on proprietary DIMMs that are inserted into eight DIMM slots set aside for its use. In configurations where there are fewer than 32 processors, the directory memory is contained within the main memory.
to the NUMAlink 2 system interconnect. The ASIC contains five major sections: the crossbar (referred to as the "XB"), the I/O interface (referred to as the "II"), the network interface (referred to as the "NI"), the processor interface (referred to as the "PI") and the memory and directory interface (referred to as the "DM"), which also serves as the memory controller. The interfaces communicate with each other via FIFO
buffers that are connected to the crossbar. When two processors are connected to the Hub ASIC, the node does not behave in a SMP
fashion. Instead, the two processors operate separately and their buses are multiplexed
over the single processor interface. This was done to save pins on the Hub ASIC. The Hub ASIC is clocked at 100 MHz and contains 900,000 gates fabricated in a five-layer metal process.
and VME64
buses can also be used, provided by XIO bridges.
A IO6 base I/O board is present in every system. It is a XIO card that provides:
The IO6G (G for Graphics) had 2 additional serial ports and keyboard/mouse ports plus the above ports. The IO6G was required on systems with the Onyx Graphics pipes(cards) to connect keyboard/mouse.
Server (computing)
In the context of client-server architecture, a server is a computer program running to serve the requests of other programs, the "clients". Thus, the "server" performs some computational task on behalf of "clients"...
developed and manufactured by SGI
Silicon Graphics
Silicon Graphics, Inc. was a manufacturer of high-performance computing solutions, including computer hardware and software, founded in 1981 by Jim Clark...
and introduced in 1996 to succeed the SGI Challenge
SGI Challenge
The Challenge, code-named Eveready and Terminator , is a family of server computers and supercomputers developed and manufactured by Silicon Graphics in the early to mid-1990s that succeeded the earlier Power series systems...
and POWER Challenge
SGI Challenge
The Challenge, code-named Eveready and Terminator , is a family of server computers and supercomputers developed and manufactured by Silicon Graphics in the early to mid-1990s that succeeded the earlier Power series systems...
. At the time of introduction, these systems ran IRIX 6.4
IRIX
IRIX is a computer operating system developed by Silicon Graphics, Inc. to run natively on their 32- and 64-bit MIPS architecture workstations and servers. It was based on UNIX System V with BSD extensions. IRIX was the first operating system to include the XFS file system.The last major version...
and later, IRIX 6.5
IRIX
IRIX is a computer operating system developed by Silicon Graphics, Inc. to run natively on their 32- and 64-bit MIPS architecture workstations and servers. It was based on UNIX System V with BSD extensions. IRIX was the first operating system to include the XFS file system.The last major version...
. A variant of the Origin 2000 with graphics capability is known as the Onyx2
SGI Onyx2
The SGI Onyx2, code name Kego, is a family of visualization systems developed and manufactured by SGI, introduced in 1996 to succeed the Onyx. The Onyx2's basic system architecture is based on the Origin 2000 servers, but with the notable inclusion of graphics hardware. In 2000, the Onyx2 was...
. An entry-level variant based on the same architecture but with a different hardware implementation is known as the Origin 200
SGI Origin 200
The SGI Origin 200, code named Speedo, is an entry-level server computer developed and manufactured by SGI, introduced in October 1996 to accompany their mid-range and high-end Origin 2000. It is based on the same architecture as the Origin 2000 but has an unrelated hardware implementation...
. The Origin 2000 was succeeded by the Origin 3000 in July 2000, and was discontinued on 30 June 2002.
Models
| Model | # of CPUs | Memory | I/O | Chassis | Introduced | Discontinued |
|---|---|---|---|---|---|---|
| Origin 2100 | 2 to 8 | Up to 16 GB | 12 XIO XIO XIO is a packet-based, high-performance computer bus employed by the SGI Origin 2000, Octane, Altix, Fuel and Tezro machines. The XIO forms a bus between high-performance system devices and the memory controller.... |
Deskside | ? | 31 May 2002 |
| Origin 2200 | 2 to 8 | Up to 16 GB | 12 XIO | Deskside | ? | 31 May 2002 |
| Origin 2400 | 8 to 32 | Up to 64 GB | 96 XIO | 1 to 4 racks | ? | 31 May 2002 |
| Origin 2800 | 32 to 128 (256 and 512 unsupported) | Up to 256 GB (512 GB unsupported) | 384 XIO | 1 to 9 racks (with Meta Router) | ? | 31 May 2002 |
Note: The highest CPU count that the SGI marketed the Origin 2000/28000 was 128 CPUs. However, three Origin 2000 models were made that were capable of using 512 CPUs and 512 GB of memory, but these were never marketed as a system to customers. One of the 512-CPU Origin 2000 series was installed at SGI's facility in Eagan, Minnesota for test purposes and the other two were sold to NASA Ames Research Center in California for specialized scientific computing. The 512-CPU Origin 2800s cost roughly $40 million each and the delivery of the Origin 3000 systems, scalable up to 512 or 1024 CPUs at a lower price point per performance, made the 512-CPU Origin 2800 obsolete.
Several customers also bought 256-CPU Origin 2000 series systems, although it was never marketed as a product by SGI either.
The largest installation of SGI Origin 2000 series was ASCII Blue Mountain at Los Alamos National Labs. It included 48 Origin 2000 series 128-CPU systems all connected via HIPPI for a total of 6144 processors. At the time it was tested, it placed second on the TOP500
TOP500
The TOP500 project ranks and details the 500 most powerful known computer systems in the world. The project was started in 1993 and publishes an updated list of the supercomputers twice a year...
list of fastest computers in the world. Note that this test was completed only with 40 nodes with 128 CPUs each and recorded a sustained 1.6 teraflops. With all nodes connected, it was able to sustain 2.1 teraflops and peak of over 2.5 teraflops.
Los Alamos also had another 12 Origin 128-CPU systems (for a total of 1536 CPUs) as part of the same testing.
The Origin 2100 is mostly the same as the other models except that it is not upgradeable to other models. (unless the router cards, etc. were replaced)
Hardware description
The Origin 2000 is based on nodes that are plugged into a backplaneBackplane
A backplane is a group of connectors connected in parallel with each other, so that each pin of each connector is linked to the same relative pin of all the other connectors forming a computer bus. It is used as a backbone to connect several printed circuit boards together to make up a complete...
. Each backplane forms a module that can contain four node boards, two router boards and twelve XIO
XIO
XIO is a packet-based, high-performance computer bus employed by the SGI Origin 2000, Octane, Altix, Fuel and Tezro machines. The XIO forms a bus between high-performance system devices and the memory controller....
options. The modules are then mounted inside a deskside enclosure or a rack. Deskside enclosures can only contain one module, while racks can contain two. In configurations with more than two modules, multiple racks are used.
| Enclosure | Width | Height | Depth | Weight |
|---|---|---|---|---|
| Deskside | 53 cm (21 inches) |
65 cm (25.5 inches) |
58 cm (23 inches) |
98 kg (215 lb) |
| Rack | 71 cm (28 inches) |
185 cm (73 inches) |
102 cm (40 inches) |
317 kg (700 lb) |
Figures specified are for maximum configurations.
Architecture
An Origin 2000 system is composed of nodes linked together by an interconnection network. It uses the distributed shared memoryDistributed shared memory
Distributed Shared Memory , in Computer Architecture is a form of memory architecture where the memories can be addressed as one address space...
S2MP (Scalable Shared-Memory Multiprocessing) architecture. The Origin 2000 uses NUMAlink (originally named CrayLink) for its system interconnect. The nodes are connected to router boards, which use NUMAlink cables to connect to other nodes through their routers. The NUMAlink's network topology is a bristled fat hypercube
Hypercube
In geometry, a hypercube is an n-dimensional analogue of a square and a cube . It is a closed, compact, convex figure whose 1-skeleton consists of groups of opposite parallel line segments aligned in each of the space's dimensions, perpendicular to each other and of the same length.An...
. In configurations with more than 64 processors, a hierarchical fat hypercube network topology is used instead. Additional NUMAlink cables, called Xpress links can be installed between unused Standard Router ports to reduce latency and increase bandwidth. Xpress links can only be used in systems that have 16 or 32 processors, as these are the only configurations with a network topology that enables unused ports to be used in such a way.
Router boards
There are four different router boards used by the Origin 2000. Each successive router board allows a larger amount of nodes to be connected.Null Router
The Null Router connects two nodes in the same module. A system using the Null Router cannot be expanded as there are no external connectors.
Star Router
The Star Router can connect up to four nodes. It is always used in conjunction with a Standard Router to function correctly.
Standard Router (Rack Router)
The Standard Router can connect up to 32 nodes. It contains the SPIDER ASIC, which serves as a router for the NUMAlink network. The SPIDER ASIC has six ports, each with a pair of unidirectional links, connected to a crossbar
Crossbar
- Structural engineering :* A primitive latch consisting of a post barring a door* The top tube of a bicycle frame* The horizontal member of many sports goals including those for hockey, association football, rugby league, rugby union and American football...
which enables the ports to communicate with each other.
Meta Router (Cray Router)
The Meta Router is used in conjunction with Standard Routers to connect more than 32 nodes. It can connect up to 64 nodes.
Origin 2000 nodes
An Origin 2000 node fits on a single 16" by 11" printed circuit boardPrinted circuit board
A printed circuit board, or PCB, is used to mechanically support and electrically connect electronic components using conductive pathways, tracks or signal traces etched from copper sheets laminated onto a non-conductive substrate. It is also referred to as printed wiring board or etched wiring...
that contains one or two processors, the main memory, the directory memory and the Hub ASIC. The node board plugs into the backplane through a 300-pad CPOP (Compression Pad-on-Pad) connector. The connector actually combines two connections, one to the NUMAlink router network and another to the XIO I/O subsystem.
Processor
Each processor and their secondary cache is contained on a HIMM (Horizontal Inline Memory Module) daughter card that plugs into the node board. At the time of introduction, the Origin 2000 used the IP27 board, featuring one or two R10000R10000
The R10000, code-named "T5", is a RISC microprocessor implementation of the MIPS IV instruction set architecture developed by MIPS Technologies, Inc. , then a division of Silicon Graphics, Inc. . The chief designers were Chris Rowen and Kenneth C. Yeager...
processors clocked at 180 MHz with 1 MB secondary cache(s). A high-end model with two 195 MHz R10000 processors with 4 MB secondary caches was also available. In February 1998, the IP31 board was introduced with two 250 MHz R10000 processors with 4 MB secondary caches. Later, the IP31 board was upgraded to support two 300, 350 or 400 MHz R12000 processors. The 300 and 400 MHz models had 8 MB L2 caches, while the 350 MHz model had 4 MB L2 caches. Near the end of its life, a variant of the IP31 board that could utilize the 500 MHz R14000 with 8 MB L2 caches was made available.
Main memory and directory memory
Each node board can support a maximum of 4 GB of memory through 16 DIMM slots by using proprietary ECC SDRAMSDRAM
Synchronous dynamic random access memory is dynamic random access memory that is synchronized with the system bus. Classic DRAM has an asynchronous interface, which means that it responds as quickly as possible to changes in control inputs...
DIMM
DIMM
A DIMM or dual in-line memory module, comprises a series of dynamic random-access memory integrated circuits. These modules are mounted on a printed circuit board and designed for use in personal computers, workstations and servers...
s with capacities of 16, 32, 64 and 256 MB. Because the memory bus is 144 bits wide (128 bits for data and 16 bits for ECC), memory modules are inserted in pairs. Directory memory, which contains information on the contents of remote caches for maintaining cache coherency
Cache coherency
In computing, cache coherence refers to the consistency of data stored in local caches of a shared resource.When clients in a system maintain caches of a common memory resource, problems may arise with inconsistent data. This is particularly true of CPUs in a multiprocessing system...
, must be used in configurations with more than 32 processors as the Origin 2000 uses a distributed shared memory model. The directory memory is contained on proprietary DIMMs that are inserted into eight DIMM slots set aside for its use. In configurations where there are fewer than 32 processors, the directory memory is contained within the main memory.
Hub ASIC
The Hub ASIC interfaces the processors, memory and XIOXIO
XIO is a packet-based, high-performance computer bus employed by the SGI Origin 2000, Octane, Altix, Fuel and Tezro machines. The XIO forms a bus between high-performance system devices and the memory controller....
to the NUMAlink 2 system interconnect. The ASIC contains five major sections: the crossbar (referred to as the "XB"), the I/O interface (referred to as the "II"), the network interface (referred to as the "NI"), the processor interface (referred to as the "PI") and the memory and directory interface (referred to as the "DM"), which also serves as the memory controller. The interfaces communicate with each other via FIFO
FIFO
FIFO is an acronym for First In, First Out, an abstraction related to ways of organizing and manipulation of data relative to time and prioritization...
buffers that are connected to the crossbar. When two processors are connected to the Hub ASIC, the node does not behave in a SMP
Symmetric multiprocessing
In computing, symmetric multiprocessing involves a multiprocessor computer hardware architecture where two or more identical processors are connected to a single shared main memory and are controlled by a single OS instance. Most common multiprocessor systems today use an SMP architecture...
fashion. Instead, the two processors operate separately and their buses are multiplexed
Multiplexing
The multiplexed signal is transmitted over a communication channel, which may be a physical transmission medium. The multiplexing divides the capacity of the low-level communication channel into several higher-level logical channels, one for each message signal or data stream to be transferred...
over the single processor interface. This was done to save pins on the Hub ASIC. The Hub ASIC is clocked at 100 MHz and contains 900,000 gates fabricated in a five-layer metal process.
I/O subsystem
The I/O subsystem is based around the Crossbow (Xbow) ASIC, which shares many similarities with the SPIDER ASIC. Since the Xbow ASIC is intended for use with the simpler XIO protocol, its hardware is also simpler, allowing the ASIC to feature eight ports, compared with the SPIDER ASIC's six ports. Two of the ports connect to the node boards, and the remaining six to XIO cards. While the I/O subsystem's native bus is XIO, PCI-XPCI-X
PCI-X, short for PCI-eXtended, is a computer bus and expansion card standard that enhances the 32-bit PCI Local Bus for higher bandwidth demanded by servers. It is a double-wide version of PCI, running at up to four times the clock speed, but is otherwise similar in electrical implementation and...
and VME64
VMEbus
VMEbus is a computer bus standard, originally developed for the Motorola 68000 line of CPUs, but later widely used for many applications and standardized by the IEC as ANSI/IEEE 1014-1987. It is physically based on Eurocard sizes, mechanicals and connectors , but uses its own signalling system,...
buses can also be used, provided by XIO bridges.
A IO6 base I/O board is present in every system. It is a XIO card that provides:
- 1 10/100BASE-TX port
- 2 Serial ports provided by dual UARTs
- 1 internal Fast 20 UltraSCSISCSISmall Computer System Interface is a set of standards for physically connecting and transferring data between computers and peripheral devices. The SCSI standards define commands, protocols, and electrical and optical interfaces. SCSI is most commonly used for hard disks and tape drives, but it...
single-ended port - 1 external wide UltraSCSISCSISmall Computer System Interface is a set of standards for physically connecting and transferring data between computers and peripheral devices. The SCSI standards define commands, protocols, and electrical and optical interfaces. SCSI is most commonly used for hard disks and tape drives, but it...
, singled ended port - 1 real-time interrupt output for frame sync
- 1 real-time interrupt input (edge triggered)
- FlashFlash memoryFlash memory is a non-volatile computer storage chip that can be electrically erased and reprogrammed. It was developed from EEPROM and must be erased in fairly large blocks before these can be rewritten with new data...
PROMPROMPROM may refer to:*Phosphate rich organic manure*Premature rupture of membranes, an obstetric term*PROM-1 land mine*Programmable read-only memory, related to electronics...
, NVRAMNVRAMNon-volatile random-access memory is random-access memory that retains its information when power is turned off, which is described technically as being non-volatile...
and real time clock
The IO6G (G for Graphics) had 2 additional serial ports and keyboard/mouse ports plus the above ports. The IO6G was required on systems with the Onyx Graphics pipes(cards) to connect keyboard/mouse.