System Management Bus
Encyclopedia
The System Management Bus (abbreviated to SMBus or SMB) is a single-ended
simple two-wire bus for the purpose of lightweight communication. Most commonly it is found in computer motherboards for communication with the power source for ON/OFF instructions.
It is derived from I²C
for communication with low-bandwidth devices on a motherboard
, especially power related chips such as a laptop's rechargeable battery subsystem (see Smart Battery Data). Other devices might include temperature, fan or voltage sensors, lid switches and clock chips. PCI add-in cards may connect to a SMBus segment.
A device can provide manufacturer information, indicate its model/part number, save its state for a suspend event, report different types of error, accept control parameters and return status. The SMBus is generally not user configurable or accessible. Although SMBus devices usually can't identify their functionality, a new PMBus coalition has extended SMBus to include conventions allowing that.
The SMBus was defined by Intel in 1995. It carries clock, data, and instructions and is based on Philips
' I²C
serial bus protocol. Its clock frequency range is 10 kHz to 100 kHz. (PMBus extends this to 400 kHz.) Its voltage levels and timings are more strictly defined than those of I²C, but devices belonging to the two systems are often successfully mixed on the same bus.
NXP devices have a higher power set of electrical characteristics than SMBus 1.0. The main difference is the current sink capability with VOL = 0.4 V.
SMBus ‘high power’ devices and I²C-bus devices will work together if the pull-up resistor is sized for 3 mA.
In I²C, a slave receiver is allowed to not acknowledge the slave address, if for example it's unable to receive because it’s performing some real time task. SMBus requires devices to acknowledge their own address always, as a mechanism to detect a removable device’s presence on the bus (battery, docking station, etc.) I²C specifies that a slave device, although it may acknowledge its own address, may decide, some time later in the transfer, that it cannot receive any more data bytes. I²C specifies that the device may
indicate this by generating the not acknowledge on the first byte to follow. Other than to indicate a slave's device-busy condition, SMBus also uses the NACK mechanism to indicate the reception of an invalid command or data. Since such a condition may occur on the last byte of the transfer, it is required that SMBus devices have the ability to generate the not acknowledge after the transfer of each byte and before the completion of the transaction. This is important because SMBus does not provide any other resend signaling. This difference in the use of the NACK signaling has implications on the specific implementation of the SMBus port, especially in devices that handle critical system data such as the SMBus host and the SBS components.
Dynamic reconfiguration of the hardware and software allow bus devices to be
‘hot-plugged’ and used immediately, without restarting the system. The devices are recognized automatically and assigned unique addresses. This advantage results in a plug-and-play user interface. In both those protocols there is a very useful distinction made between a System Host and all the other devices in the system that can have the names and functions of masters or slaves.
This explains the minimum clock frequency of 10 kHz to prevent locking up the bus. I²C can be a ‘DC’ bus, meaning that a slave device stretches the master clock when performing some routine while the master is accessing it. This will notify to the master that the slave is busy but does not want to lose the communication. The slave device will allow continuation after its task is complete. There is no limit in the I²C-bus protocol as to how long this delay can be, whereas for an SMBus system, it would be limited to 35 ms.
SMBus protocol just assumes that if something takes too long, then it means that there is a problem on the bus and that all devices must reset in order to clear this mode. Slave devices are not then allowed to hold the clock LOW too long.
, calculated over the entire message including the address and read/write bit. The polynomial used is x8+x2+x+1 (the CRC-8-ATM
HEC
algorithm, initialized to zero).
signal called SMBALERT#, which can be used by slaves to tell the host to ask its slaves about events of interest.
SMBus also defines a less common "Host Notify Protocol", providing similar notifications but passing more data and building on the I²C multi-master mode.
, OpenBSD
, NetBSD
, DragonFly BSD
, Linux
, Windows 2000
and newer server editions, and Windows XP
and newer desktop editions.
Single-ended signalling
Single-ended signaling is the simplest and most commonly used method of transmitting electrical signals over wires. One wire carries a varying voltage that represents the signal, while the other wire is connected to a reference voltage, usually ground....
simple two-wire bus for the purpose of lightweight communication. Most commonly it is found in computer motherboards for communication with the power source for ON/OFF instructions.
It is derived from I²C
I²C
I²C is a multi-master serial single-ended computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, cellphone, or other electronic device. Since the mid 1990s, several competitors I²C ("i-squared cee" or "i-two cee"; Inter-Integrated Circuit;...
for communication with low-bandwidth devices on a motherboard
Motherboard
In personal computers, a motherboard is the central printed circuit board in many modern computers and holds many of the crucial components of the system, providing connectors for other peripherals. The motherboard is sometimes alternatively known as the mainboard, system board, or, on Apple...
, especially power related chips such as a laptop's rechargeable battery subsystem (see Smart Battery Data). Other devices might include temperature, fan or voltage sensors, lid switches and clock chips. PCI add-in cards may connect to a SMBus segment.
A device can provide manufacturer information, indicate its model/part number, save its state for a suspend event, report different types of error, accept control parameters and return status. The SMBus is generally not user configurable or accessible. Although SMBus devices usually can't identify their functionality, a new PMBus coalition has extended SMBus to include conventions allowing that.
The SMBus was defined by Intel in 1995. It carries clock, data, and instructions and is based on Philips
Philips
Koninklijke Philips Electronics N.V. , more commonly known as Philips, is a multinational Dutch electronics company....
' I²C
I²C
I²C is a multi-master serial single-ended computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, cellphone, or other electronic device. Since the mid 1990s, several competitors I²C ("i-squared cee" or "i-two cee"; Inter-Integrated Circuit;...
serial bus protocol. Its clock frequency range is 10 kHz to 100 kHz. (PMBus extends this to 400 kHz.) Its voltage levels and timings are more strictly defined than those of I²C, but devices belonging to the two systems are often successfully mixed on the same bus.
SMBus/I²C Interoperability
While SMBus is derived from I²C, there are several major differences between the specifications of the two busses in the areas of electricals, timing, protocols and operating modes.Input Voltage (VIL and VIH)
When mixing devices, the I²C specification defines the VDD to be 5.0 V ±10% and the fixed input levels to be 1.5 and 3.0 V. Instead of relating the bus input levels to VDD, SMBus defines them to be fixed at 0.8 and 2.1 V. This SMBus specification allows for bus implementations with VDD ranging from 3 to 5 V.Sink Current (IOL)
SMBus has a ‘High Power’ version 2.0 that includes a 4 mA sink current that cannot be driven by I²C chips unless the pull-up resistor is sized to I²C-bus levels.NXP devices have a higher power set of electrical characteristics than SMBus 1.0. The main difference is the current sink capability with VOL = 0.4 V.
- SMBus low power = 350 μA
- SMBus high power = 4 mA
- I²C-bus = 3 mA
SMBus ‘high power’ devices and I²C-bus devices will work together if the pull-up resistor is sized for 3 mA.
Frequency (FMAX and FMIN)
The SMBus clock is defined from 10–100 kHz while I²C can be 0–100 kHz, 0–400 kHz, 0–1 MHz and 0–3.4 MHz, depending on the mode. This means that an I²C bus running at less than 10 kHz will not be SMBus compliant since the SMBus devices may time out. Many SMBus devices will however support lower frequencies.Timing
- SMBus defines a clock low time-out, TTIMEOUT of 35 ms. I²C does not specify any timeout limit.
- SMBus specifies TLOW: SEXT as the cumulative clock low extend time for a slave device. I²C does not have a similar specification.
- SMBus specifies TLOW: MEXT as the cumulative clock low extend time for a master device. Again I²C does not have a similar specification.
- SMBus defines both rise and fall time of bus signals. I²C does not.
- The SMBus time-out specifications do not preclude I²C devices co-operating reliably on the SMBus. It is the responsibility of the designer to ensure that I²C devices are not going to violate these bus timing parameters.
ACK and NACK usage
There are the following differences in the use of the NACK bus signaling:In I²C, a slave receiver is allowed to not acknowledge the slave address, if for example it's unable to receive because it’s performing some real time task. SMBus requires devices to acknowledge their own address always, as a mechanism to detect a removable device’s presence on the bus (battery, docking station, etc.) I²C specifies that a slave device, although it may acknowledge its own address, may decide, some time later in the transfer, that it cannot receive any more data bytes. I²C specifies that the device may
indicate this by generating the not acknowledge on the first byte to follow. Other than to indicate a slave's device-busy condition, SMBus also uses the NACK mechanism to indicate the reception of an invalid command or data. Since such a condition may occur on the last byte of the transfer, it is required that SMBus devices have the ability to generate the not acknowledge after the transfer of each byte and before the completion of the transaction. This is important because SMBus does not provide any other resend signaling. This difference in the use of the NACK signaling has implications on the specific implementation of the SMBus port, especially in devices that handle critical system data such as the SMBus host and the SBS components.
SMBus protocols
Each message transaction on SMBus follows the format of one of the defined SMBus protocols. The SMBus protocols are a subset of the data transfer formats defined in the I²C specifications. I²C devices that can be accessed through one of the SMBus protocols are compatible with the SMBus specifications. I²C devices that do not adhere to these protocols cannot be accessed by standard methods as defined in the SMBus and ACPI specifications.Address Resolution Protocol
The SMBus uses I²C hardware and I²C hardware addressing, but adds second-level software for building special systems. In particular its specifications include an Address Resolution Protocol that can make dynamic address allocations.Dynamic reconfiguration of the hardware and software allow bus devices to be
‘hot-plugged’ and used immediately, without restarting the system. The devices are recognized automatically and assigned unique addresses. This advantage results in a plug-and-play user interface. In both those protocols there is a very useful distinction made between a System Host and all the other devices in the system that can have the names and functions of masters or slaves.
Time-out feature
SMBus has a time-out feature which resets devices if a communication takes too long.This explains the minimum clock frequency of 10 kHz to prevent locking up the bus. I²C can be a ‘DC’ bus, meaning that a slave device stretches the master clock when performing some routine while the master is accessing it. This will notify to the master that the slave is busy but does not want to lose the communication. The slave device will allow continuation after its task is complete. There is no limit in the I²C-bus protocol as to how long this delay can be, whereas for an SMBus system, it would be limited to 35 ms.
SMBus protocol just assumes that if something takes too long, then it means that there is a problem on the bus and that all devices must reset in order to clear this mode. Slave devices are not then allowed to hold the clock LOW too long.
Packet Error Checking
SMBus 2.0 and 1.1 allow enabling Packet Error Checking (PEC). In that mode, a PEC (packet error code) byte is appended at the end of each transaction. The byte is calculated as CRC-8 checksumChecksum
A checksum or hash sum is a fixed-size datum computed from an arbitrary block of digital data for the purpose of detecting accidental errors that may have been introduced during its transmission or storage. The integrity of the data can be checked at any later time by recomputing the checksum and...
, calculated over the entire message including the address and read/write bit. The polynomial used is x8+x2+x+1 (the CRC-8-ATM
Asynchronous Transfer Mode
Asynchronous Transfer Mode is a standard switching technique designed to unify telecommunication and computer networks. It uses asynchronous time-division multiplexing, and it encodes data into small, fixed-sized cells. This differs from approaches such as the Internet Protocol or Ethernet that...
HEC
Header Error Correction
This is a bit error detection and correction mechanism used in data transmitter and receiver.The Header Error Control is the last field in the Asynchronous Transfer Mode cell consisting of an 8-bit CRC of the cell's header only....
algorithm, initialized to zero).
SMBALERT#
The SMBus has an extra optional shared interruptInterrupt
In computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution....
signal called SMBALERT#, which can be used by slaves to tell the host to ask its slaves about events of interest.
SMBus also defines a less common "Host Notify Protocol", providing similar notifications but passing more data and building on the I²C multi-master mode.
SMBus Support
SMBus devices are supported by FreeBSDFreeBSD
FreeBSD is a free Unix-like operating system descended from AT&T UNIX via BSD UNIX. Although for legal reasons FreeBSD cannot be called “UNIX”, as the direct descendant of BSD UNIX , FreeBSD’s internals and system APIs are UNIX-compliant...
, OpenBSD
OpenBSD
OpenBSD is a Unix-like computer operating system descended from Berkeley Software Distribution , a Unix derivative developed at the University of California, Berkeley. It was forked from NetBSD by project leader Theo de Raadt in late 1995...
, NetBSD
NetBSD
NetBSD is a freely available open source version of the Berkeley Software Distribution Unix operating system. It was the second open source BSD descendant to be formally released, after 386BSD, and continues to be actively developed. The NetBSD project is primarily focused on high quality design,...
, DragonFly BSD
DragonFly BSD
DragonFly BSD is a free Unix-like operating system created as a fork of FreeBSD 4.8. Matthew Dillon, an Amiga developer in the late 1980s and early 1990s and a FreeBSD developer between 1994 and 2003, began work on DragonFly BSD in June 2003 and announced it on the FreeBSD mailing lists on July...
, Linux
Linux
Linux is a Unix-like computer operating system assembled under the model of free and open source software development and distribution. The defining component of any Linux system is the Linux kernel, an operating system kernel first released October 5, 1991 by Linus Torvalds...
, Windows 2000
Windows 2000
Windows 2000 is a line of operating systems produced by Microsoft for use on personal computers, business desktops, laptops, and servers. Windows 2000 was released to manufacturing on 15 December 1999 and launched to retail on 17 February 2000. It is the successor to Windows NT 4.0, and is the...
and newer server editions, and Windows XP
Windows XP
Windows XP is an operating system produced by Microsoft for use on personal computers, including home and business desktops, laptops and media centers. First released to computer manufacturers on August 24, 2001, it is the second most popular version of Windows, based on installed user base...
and newer desktop editions.
See also
- I²CI²CI²C is a multi-master serial single-ended computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, cellphone, or other electronic device. Since the mid 1990s, several competitors I²C ("i-squared cee" or "i-two cee"; Inter-Integrated Circuit;...
(I2C) - Power Management Bus (PMBus)
- Advanced Configuration and Power InterfaceAdvanced Configuration and Power InterfaceIn computing, the Advanced Configuration and Power Interface specification provides an open standard for device configuration and power management by the operating system....
(ACPI) - List of network buses